arch/arm/include/asm/arch-rockchip/cru_px30.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
   4  */
   5 #ifndef _ASM_ARCH_CRU_PX30_H
   6 #define _ASM_ARCH_CRU_PX30_H
   7
   8 #define MHz             1000000
   9 #define KHz             1000
  10 #define OSC_HZ          (24 * MHz)
  11
  12 #define APLL_HZ         (600 * MHz)
  13 #define GPLL_HZ         (1200 * MHz)
  14 #define NPLL_HZ         (1188 * MHz)
  15 #define ACLK_BUS_HZ     (200 * MHz)
  16 #define HCLK_BUS_HZ     (150 * MHz)
  17 #define PCLK_BUS_HZ     (100 * MHz)
  18 #define ACLK_PERI_HZ    (200 * MHz)
  19 #define HCLK_PERI_HZ    (150 * MHz)
  20 #define PCLK_PMU_HZ     (100 * MHz)
  21
  22 /* PX30 pll id */
  23 enum px30_pll_id {
  24         APLL,
  25         DPLL,
  26         CPLL,
  27         NPLL,
  28         GPLL,
  29         PLL_COUNT,
  30 };
  31
  32 struct px30_clk_priv {
  33         struct px30_cru *cru;
  34         ulong gpll_hz;
  35 };
  36
  37 struct px30_pmuclk_priv {
  38         struct px30_pmucru *pmucru;
  39         ulong gpll_hz;
  40 };
  41
  42 struct px30_pll {
  43         unsigned int con0;
  44         unsigned int con1;
  45         unsigned int con2;
  46         unsigned int con3;
  47         unsigned int con4;
  48         unsigned int reserved0[3];
  49 };
  50
  51 struct px30_cru {
  52         struct px30_pll pll[4];
  53         unsigned int reserved1[8];
  54         unsigned int mode;
  55         unsigned int misc;
  56         unsigned int reserved2[2];
  57         unsigned int glb_cnt_th;
  58         unsigned int glb_rst_st;
  59         unsigned int glb_srst_fst;
  60         unsigned int glb_srst_snd;
  61         unsigned int glb_rst_con;
  62         unsigned int reserved3[7];
  63         unsigned int hwffc_con0;
  64         unsigned int reserved4;
  65         unsigned int hwffc_th;
  66         unsigned int hwffc_intst;
  67         unsigned int apll_con0_s;
  68         unsigned int apll_con1_s;
  69         unsigned int clksel_con0_s;
  70         unsigned int reserved5;
  71         unsigned int clksel_con[60];
  72         unsigned int reserved6[4];
  73         unsigned int clkgate_con[18];
  74         unsigned int reserved7[(0x280 - 0x244) / 4 - 1];
  75         unsigned int ssgtbl[32];
  76         unsigned int softrst_con[12];
  77         unsigned int reserved8[(0x380 - 0x32c) / 4 - 1];
  78         unsigned int sdmmc_con[2];
  79         unsigned int sdio_con[2];
  80         unsigned int emmc_con[2];
  81         unsigned int reserved9[(0x400 - 0x394) / 4 - 1];
  82         unsigned int autocs_con[8];
  83 };
  84
  85 check_member(px30_cru, autocs_con[7], 0x41c);
  86
  87 struct px30_pmucru {
  88         struct px30_pll pll;
  89         unsigned int pmu_mode;
  90         unsigned int reserved1[7];
  91         unsigned int pmu_clksel_con[6];
  92         unsigned int reserved2[10];
  93         unsigned int pmu_clkgate_con[2];
  94         unsigned int reserved3[14];
  95         unsigned int pmu_autocs_con[2];
  96 };
  97
  98 check_member(px30_pmucru, pmu_autocs_con[1], 0xc4);
  99
 100 struct pll_rate_table {
 101         unsigned long rate;
 102         unsigned int fbdiv;
 103         unsigned int postdiv1;
 104         unsigned int refdiv;
 105         unsigned int postdiv2;
 106         unsigned int dsmpd;
 107         unsigned int frac;
 108 };
 109
 110 struct cpu_rate_table {
 111         unsigned long rate;
 112         unsigned int aclk_div;
 113         unsigned int pclk_div;
 114 };
 115
 116 enum {
 117         /* PLLCON0*/
 118         PLL_BP_SHIFT            = 15,
 119         PLL_POSTDIV1_SHIFT      = 12,
 120         PLL_POSTDIV1_MASK       = 7 << PLL_POSTDIV1_SHIFT,
 121         PLL_FBDIV_SHIFT         = 0,
 122         PLL_FBDIV_MASK          = 0xfff,
 123
 124         /* PLLCON1 */
 125         PLL_PDSEL_SHIFT         = 15,
 126         PLL_PD1_SHIFT           = 14,
 127         PLL_PD_SHIFT            = 13,
 128         PLL_PD_MASK             = 1 << PLL_PD_SHIFT,
 129         PLL_DSMPD_SHIFT         = 12,
 130         PLL_DSMPD_MASK          = 1 << PLL_DSMPD_SHIFT,
 131         PLL_LOCK_STATUS_SHIFT   = 10,
 132         PLL_LOCK_STATUS_MASK    = 1 << PLL_LOCK_STATUS_SHIFT,
 133         PLL_POSTDIV2_SHIFT      = 6,
 134         PLL_POSTDIV2_MASK       = 7 << PLL_POSTDIV2_SHIFT,
 135         PLL_REFDIV_SHIFT        = 0,
 136         PLL_REFDIV_MASK         = 0x3f,
 137
 138         /* PLLCON2 */
 139         PLL_FOUT4PHASEPD_SHIFT  = 27,
 140         PLL_FOUTVCOPD_SHIFT     = 26,
 141         PLL_FOUTPOSTDIVPD_SHIFT = 25,
 142         PLL_DACPD_SHIFT         = 24,
 143         PLL_FRAC_DIV    = 0xffffff,
 144
 145         /* CRU_MODE */
 146         PLLMUX_FROM_XIN24M      = 0,
 147         PLLMUX_FROM_PLL,
 148         PLLMUX_FROM_RTC32K,
 149         USBPHY480M_MODE_SHIFT   = 8,
 150         USBPHY480M_MODE_MASK    = 3 << USBPHY480M_MODE_SHIFT,
 151         NPLL_MODE_SHIFT         = 6,
 152         NPLL_MODE_MASK          = 3 << NPLL_MODE_SHIFT,
 153         DPLL_MODE_SHIFT         = 4,
 154         DPLL_MODE_MASK          = 3 << DPLL_MODE_SHIFT,
 155         CPLL_MODE_SHIFT         = 2,
 156         CPLL_MODE_MASK          = 3 << CPLL_MODE_SHIFT,
 157         APLL_MODE_SHIFT         = 0,
 158         APLL_MODE_MASK          = 3 << APLL_MODE_SHIFT,
 159
 160         /* CRU_CLK_SEL0_CON */
 161         CORE_ACLK_DIV_SHIFT     = 12,
 162         CORE_ACLK_DIV_MASK      = 0x07 << CORE_ACLK_DIV_SHIFT,
 163         CORE_DBG_DIV_SHIFT      = 8,
 164         CORE_DBG_DIV_MASK       = 0x03 << CORE_DBG_DIV_SHIFT,
 165         CORE_CLK_PLL_SEL_SHIFT  = 7,
 166         CORE_CLK_PLL_SEL_MASK   = 1 << CORE_CLK_PLL_SEL_SHIFT,
 167         CORE_CLK_PLL_SEL_APLL   = 0,
 168         CORE_CLK_PLL_SEL_GPLL,
 169         CORE_DIV_CON_SHIFT      = 0,
 170         CORE_DIV_CON_MASK       = 0x0f << CORE_DIV_CON_SHIFT,
 171
 172         /* CRU_CLK_SEL3_CON */
 173         ACLK_VO_PLL_SHIFT       = 6,
 174         ACLK_VO_PLL_MASK        = 0x3 << ACLK_VO_PLL_SHIFT,
 175         ACLK_VO_SEL_GPLL        = 0,
 176         ACLK_VO_SEL_CPLL,
 177         ACLK_VO_SEL_NPLL,
 178         ACLK_VO_DIV_SHIFT       = 0,
 179         ACLK_VO_DIV_MASK        = 0x1f << ACLK_VO_DIV_SHIFT,
 180
 181         /* CRU_CLK_SEL5_CON */
 182         DCLK_VOPB_SEL_SHIFT     = 14,
 183         DCLK_VOPB_SEL_MASK      = 0x3 << DCLK_VOPB_SEL_SHIFT,
 184         DCLK_VOPB_SEL_DIVOUT    = 0,
 185         DCLK_VOPB_SEL_FRACOUT,
 186         DCLK_VOPB_SEL_24M,
 187         DCLK_VOPB_PLL_SEL_SHIFT = 11,
 188         DCLK_VOPB_PLL_SEL_MASK  = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT,
 189         DCLK_VOPB_PLL_SEL_CPLL  = 0,
 190         DCLK_VOPB_PLL_SEL_NPLL,
 191         DCLK_VOPB_DIV_SHIFT     = 0,
 192         DCLK_VOPB_DIV_MASK      = 0xff,
 193
 194         /* CRU_CLK_SEL8_CON */
 195         DCLK_VOPL_SEL_SHIFT     = 14,
 196         DCLK_VOPL_SEL_MASK      = 0x3 << DCLK_VOPL_SEL_SHIFT,
 197         DCLK_VOPL_SEL_DIVOUT    = 0,
 198         DCLK_VOPL_SEL_FRACOUT,
 199         DCLK_VOPL_SEL_24M,
 200         DCLK_VOPL_PLL_SEL_SHIFT = 11,
 201         DCLK_VOPL_PLL_SEL_MASK  = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT,
 202         DCLK_VOPL_PLL_SEL_NPLL  = 0,
 203         DCLK_VOPL_PLL_SEL_CPLL,
 204         DCLK_VOPL_DIV_SHIFT     = 0,
 205         DCLK_VOPL_DIV_MASK      = 0xff,
 206
 207         /* CRU_CLK_SEL14_CON */
 208         PERI_PLL_SEL_SHIFT      = 15,
 209         PERI_PLL_SEL_MASK       = 3 << PERI_PLL_SEL_SHIFT,
 210         PERI_PLL_GPLL           = 0,
 211         PERI_PLL_CPLL,
 212         PERI_HCLK_DIV_SHIFT     = 8,
 213         PERI_HCLK_DIV_MASK      = 0x1f << PERI_HCLK_DIV_SHIFT,
 214         PERI_ACLK_DIV_SHIFT     = 0,
 215         PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 216
 217         /* CRU_CLKSEL15_CON */
 218         NANDC_CLK_SEL_SHIFT     = 15,
 219         NANDC_CLK_SEL_MASK      = 0x1 << NANDC_CLK_SEL_SHIFT,
 220         NANDC_CLK_SEL_NANDC     = 0,
 221         NANDC_CLK_SEL_NANDC_DIV50,
 222         NANDC_DIV50_SHIFT       = 8,
 223         NANDC_DIV50_MASK        = 0x1f << NANDC_DIV50_SHIFT,
 224         NANDC_PLL_SHIFT         = 6,
 225         NANDC_PLL_MASK          = 0x3 << NANDC_PLL_SHIFT,
 226         NANDC_SEL_GPLL          = 0,
 227         NANDC_SEL_CPLL,
 228         NANDC_SEL_NPLL,
 229         NANDC_DIV_SHIFT         = 0,
 230         NANDC_DIV_MASK          = 0x1f << NANDC_DIV_SHIFT,
 231
 232         /* CRU_CLKSEL20_CON */
 233         EMMC_PLL_SHIFT          = 14,
 234         EMMC_PLL_MASK           = 3 << EMMC_PLL_SHIFT,
 235         EMMC_SEL_GPLL           = 0,
 236         EMMC_SEL_CPLL,
 237         EMMC_SEL_NPLL,
 238         EMMC_SEL_24M,
 239         EMMC_DIV_SHIFT          = 0,
 240         EMMC_DIV_MASK           = 0xff << EMMC_DIV_SHIFT,
 241
 242         /* CRU_CLKSEL21_CON */
 243         EMMC_CLK_SEL_SHIFT      = 15,
 244         EMMC_CLK_SEL_MASK       = 1 << EMMC_CLK_SEL_SHIFT,
 245         EMMC_CLK_SEL_EMMC       = 0,
 246         EMMC_CLK_SEL_EMMC_DIV50,
 247         EMMC_DIV50_SHIFT        = 0,
 248         EMMC_DIV50_MASK         = 0xff << EMMC_DIV_SHIFT,
 249
 250         /* CRU_CLKSEL22_CON */
 251         GMAC_PLL_SEL_SHIFT      = 14,
 252         GMAC_PLL_SEL_MASK       = 3 << GMAC_PLL_SEL_SHIFT,
 253         GMAC_PLL_SEL_GPLL       = 0,
 254         GMAC_PLL_SEL_CPLL,
 255         GMAC_PLL_SEL_NPLL,
 256         CLK_GMAC_DIV_SHIFT      = 8,
 257         CLK_GMAC_DIV_MASK       = 0x1f << CLK_GMAC_DIV_SHIFT,
 258         SFC_PLL_SEL_SHIFT       = 7,
 259         SFC_PLL_SEL_MASK        = 1 << SFC_PLL_SEL_SHIFT,
 260         SFC_DIV_CON_SHIFT       = 0,
 261         SFC_DIV_CON_MASK        = 0x7f,
 262
 263         /* CRU_CLK_SEL23_CON */
 264         BUS_PLL_SEL_SHIFT       = 15,
 265         BUS_PLL_SEL_MASK        = 1 << BUS_PLL_SEL_SHIFT,
 266         BUS_PLL_SEL_GPLL        = 0,
 267         BUS_PLL_SEL_CPLL,
 268         BUS_ACLK_DIV_SHIFT      = 8,
 269         BUS_ACLK_DIV_MASK       = 0x1f << BUS_ACLK_DIV_SHIFT,
 270         RMII_CLK_SEL_SHIFT      = 7,
 271         RMII_CLK_SEL_MASK       = 1 << RMII_CLK_SEL_SHIFT,
 272         RMII_CLK_SEL_10M        = 0,
 273         RMII_CLK_SEL_100M,
 274         RMII_EXTCLK_SEL_SHIFT   = 6,
 275         RMII_EXTCLK_SEL_MASK    = 1 << RMII_EXTCLK_SEL_SHIFT,
 276         RMII_EXTCLK_SEL_INT     = 0,
 277         RMII_EXTCLK_SEL_EXT,
 278         PCLK_GMAC_DIV_SHIFT     = 0,
 279         PCLK_GMAC_DIV_MASK      = 0x0f << PCLK_GMAC_DIV_SHIFT,
 280
 281         /* CRU_CLK_SEL24_CON */
 282         BUS_PCLK_DIV_SHIFT      = 8,
 283         BUS_PCLK_DIV_MASK       = 3 << BUS_PCLK_DIV_SHIFT,
 284         BUS_HCLK_DIV_SHIFT      = 0,
 285         BUS_HCLK_DIV_MASK       = 0x1f << BUS_HCLK_DIV_SHIFT,
 286
 287         /* CRU_CLK_SEL25_CON */
 288         CRYPTO_APK_SEL_SHIFT    = 14,
 289         CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
 290         CRYPTO_PLL_SEL_GPLL     = 0,
 291         CRYPTO_PLL_SEL_CPLL,
 292         CRYPTO_PLL_SEL_NPLL     = 0,
 293         CRYPTO_APK_DIV_SHIFT    = 8,
 294         CRYPTO_APK_DIV_MASK     = 0x1f << CRYPTO_APK_DIV_SHIFT,
 295         CRYPTO_PLL_SEL_SHIFT    = 6,
 296         CRYPTO_PLL_SEL_MASK     = 3 << CRYPTO_PLL_SEL_SHIFT,
 297         CRYPTO_DIV_SHIFT        = 0,
 298         CRYPTO_DIV_MASK         = 0x1f << CRYPTO_DIV_SHIFT,
 299
 300         /* CRU_CLK_SEL30_CON */
 301         CLK_I2S1_DIV_CON_MASK   = 0x7f,
 302         CLK_I2S1_PLL_SEL_MASK   = 0X1 << 8,
 303         CLK_I2S1_PLL_SEL_GPLL   = 0X0 << 8,
 304         CLK_I2S1_PLL_SEL_NPLL   = 0X1 << 8,
 305         CLK_I2S1_SEL_MASK       = 0x3 << 10,
 306         CLK_I2S1_SEL_I2S1       = 0x0 << 10,
 307         CLK_I2S1_SEL_FRAC       = 0x1 << 10,
 308         CLK_I2S1_SEL_MCLK_IN    = 0x2 << 10,
 309         CLK_I2S1_SEL_OSC        = 0x3 << 10,
 310         CLK_I2S1_OUT_SEL_MASK   = 0x1 << 15,
 311         CLK_I2S1_OUT_SEL_I2S1   = 0x0 << 15,
 312         CLK_I2S1_OUT_SEL_OSC    = 0x1 << 15,
 313
 314         /* CRU_CLK_SEL31_CON */
 315         CLK_I2S1_FRAC_NUMERATOR_SHIFT   = 16,
 316         CLK_I2S1_FRAC_NUMERATOR_MASK    = 0xffff << 16,
 317         CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0,
 318         CLK_I2S1_FRAC_DENOMINATOR_MASK  = 0xffff,
 319
 320         /* CRU_CLK_SEL34_CON */
 321         UART1_PLL_SEL_SHIFT     = 14,
 322         UART1_PLL_SEL_MASK      = 3 << UART1_PLL_SEL_SHIFT,
 323         UART1_PLL_SEL_GPLL      = 0,
 324         UART1_PLL_SEL_24M,
 325         UART1_PLL_SEL_480M,
 326         UART1_PLL_SEL_NPLL,
 327         UART1_DIV_CON_SHIFT     = 0,
 328         UART1_DIV_CON_MASK      = 0x1f << UART1_DIV_CON_SHIFT,
 329
 330         /* CRU_CLK_SEL35_CON */
 331         UART1_CLK_SEL_SHIFT     = 14,
 332         UART1_CLK_SEL_MASK      = 3 << UART1_PLL_SEL_SHIFT,
 333         UART1_CLK_SEL_UART1     = 0,
 334         UART1_CLK_SEL_UART1_NP5,
 335         UART1_CLK_SEL_UART1_FRAC,
 336         UART1_DIVNP5_SHIFT      = 0,
 337         UART1_DIVNP5_MASK       = 0x1f << UART1_DIVNP5_SHIFT,
 338
 339         /* CRU_CLK_SEL37_CON */
 340         UART2_PLL_SEL_SHIFT     = 14,
 341         UART2_PLL_SEL_MASK      = 3 << UART2_PLL_SEL_SHIFT,
 342         UART2_PLL_SEL_GPLL      = 0,
 343         UART2_PLL_SEL_24M,
 344         UART2_PLL_SEL_480M,
 345         UART2_PLL_SEL_NPLL,
 346         UART2_DIV_CON_SHIFT     = 0,
 347         UART2_DIV_CON_MASK      = 0x1f << UART2_DIV_CON_SHIFT,
 348
 349         /* CRU_CLK_SEL38_CON */
 350         UART2_CLK_SEL_SHIFT     = 14,
 351         UART2_CLK_SEL_MASK      = 3 << UART2_PLL_SEL_SHIFT,
 352         UART2_CLK_SEL_UART2     = 0,
 353         UART2_CLK_SEL_UART2_NP5,
 354         UART2_CLK_SEL_UART2_FRAC,
 355         UART2_DIVNP5_SHIFT      = 0,
 356         UART2_DIVNP5_MASK       = 0x1f << UART2_DIVNP5_SHIFT,
 357
 358         /* CRU_CLK_SEL40_CON */
 359         UART3_PLL_SEL_SHIFT     = 14,
 360         UART3_PLL_SEL_MASK      = 3 << UART3_PLL_SEL_SHIFT,
 361         UART3_PLL_SEL_GPLL      = 0,
 362         UART3_PLL_SEL_24M,
 363         UART3_PLL_SEL_480M,
 364         UART3_PLL_SEL_NPLL,
 365         UART3_DIV_CON_SHIFT     = 0,
 366         UART3_DIV_CON_MASK      = 0x1f << UART3_DIV_CON_SHIFT,
 367
 368         /* CRU_CLK_SEL41_CON */
 369         UART3_CLK_SEL_SHIFT     = 14,
 370         UART3_CLK_SEL_MASK      = 3 << UART3_PLL_SEL_SHIFT,
 371         UART3_CLK_SEL_UART3     = 0,
 372         UART3_CLK_SEL_UART3_NP5,
 373         UART3_CLK_SEL_UART3_FRAC,
 374         UART3_DIVNP5_SHIFT      = 0,
 375         UART3_DIVNP5_MASK       = 0x1f << UART3_DIVNP5_SHIFT,
 376
 377         /* CRU_CLK_SEL46_CON */
 378         UART5_PLL_SEL_SHIFT     = 14,
 379         UART5_PLL_SEL_MASK      = 3 << UART5_PLL_SEL_SHIFT,
 380         UART5_PLL_SEL_GPLL      = 0,
 381         UART5_PLL_SEL_24M,
 382         UART5_PLL_SEL_480M,
 383         UART5_PLL_SEL_NPLL,
 384         UART5_DIV_CON_SHIFT     = 0,
 385         UART5_DIV_CON_MASK      = 0x1f << UART5_DIV_CON_SHIFT,
 386
 387         /* CRU_CLK_SEL47_CON */
 388         UART5_CLK_SEL_SHIFT     = 14,
 389         UART5_CLK_SEL_MASK      = 3 << UART5_PLL_SEL_SHIFT,
 390         UART5_CLK_SEL_UART5     = 0,
 391         UART5_CLK_SEL_UART5_NP5,
 392         UART5_CLK_SEL_UART5_FRAC,
 393         UART5_DIVNP5_SHIFT      = 0,
 394         UART5_DIVNP5_MASK       = 0x1f << UART5_DIVNP5_SHIFT,
 395
 396         /* CRU_CLK_SEL49_CON */
 397         CLK_I2C_PLL_SEL_GPLL            = 0,
 398         CLK_I2C_PLL_SEL_24M,
 399         CLK_I2C_DIV_CON_MASK            = 0x7f,
 400         CLK_I2C_PLL_SEL_MASK            = 1,
 401         CLK_I2C1_PLL_SEL_SHIFT          = 15,
 402         CLK_I2C1_DIV_CON_SHIFT          = 8,
 403         CLK_I2C0_PLL_SEL_SHIFT          = 7,
 404         CLK_I2C0_DIV_CON_SHIFT          = 0,
 405
 406         /* CRU_CLK_SEL50_CON */
 407         CLK_I2C3_PLL_SEL_SHIFT          = 15,
 408         CLK_I2C3_DIV_CON_SHIFT          = 8,
 409         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 410         CLK_I2C2_DIV_CON_SHIFT          = 0,
 411
 412         /* CRU_CLK_SEL52_CON */
 413         CLK_PWM_PLL_SEL_GPLL            = 0,
 414         CLK_PWM_PLL_SEL_24M,
 415         CLK_PWM_DIV_CON_MASK            = 0x7f,
 416         CLK_PWM_PLL_SEL_MASK            = 1,
 417         CLK_PWM1_PLL_SEL_SHIFT          = 15,
 418         CLK_PWM1_DIV_CON_SHIFT          = 8,
 419         CLK_PWM0_PLL_SEL_SHIFT          = 7,
 420         CLK_PWM0_DIV_CON_SHIFT          = 0,
 421
 422         /* CRU_CLK_SEL53_CON */
 423         CLK_SPI_PLL_SEL_GPLL            = 0,
 424         CLK_SPI_PLL_SEL_24M,
 425         CLK_SPI_DIV_CON_MASK            = 0x7f,
 426         CLK_SPI_PLL_SEL_MASK            = 1,
 427         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 428         CLK_SPI1_DIV_CON_SHIFT          = 8,
 429         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 430         CLK_SPI0_DIV_CON_SHIFT          = 0,
 431
 432         /* CRU_CLK_SEL55_CON */
 433         CLK_SARADC_DIV_CON_SHIFT        = 0,
 434         CLK_SARADC_DIV_CON_MASK         = 0x7ff,
 435
 436         /* CRU_CLK_GATE10_CON */
 437         CLK_I2S1_OUT_MCLK_PAD_MASK      = 0x1 << 9,
 438         CLK_I2S1_OUT_MCLK_PAD_ENABLE    = 0x1 << 9,
 439         CLK_I2S1_OUT_MCLK_PAD_DISABLE   = 0x0 << 9,
 440
 441         /* CRU_PMU_MODE */
 442         GPLL_MODE_SHIFT                 = 0,
 443         GPLL_MODE_MASK                  = 3 << GPLL_MODE_SHIFT,
 444
 445         /* CRU_PMU_CLK_SEL0_CON */
 446         CLK_PMU_PCLK_DIV_SHIFT          = 0,
 447         CLK_PMU_PCLK_DIV_MASK           = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
 448 };
 449 #endif