arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

   1 /*
   2  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
   8 #define __ARCH_FSL_LSCH2_IMMAP_H__
   9
  10 #include <fsl_immap.h>
  11
  12 #define CONFIG_SYS_IMMR                         0x01000000
  13 #define CONFIG_SYS_DCSRBAR                      0x20000000
  14 #define CONFIG_SYS_DCSR_DCFG_ADDR       (CONFIG_SYS_DCSRBAR + 0x00140000)
  15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR    (CONFIG_SYS_DCSRBAR + 0x02008040)
  16
  17 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  18 #define CONFIG_SYS_CCI400_ADDR                  (CONFIG_SYS_IMMR + 0x00180000)
  19 #define CONFIG_SYS_GIC400_ADDR                  (CONFIG_SYS_IMMR + 0x00400000)
  20 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x00530000)
  21 #define SYS_FSL_QSPI_ADDR                       (CONFIG_SYS_IMMR + 0x00550000)
  22 #define CONFIG_SYS_FSL_ESDHC_ADDR               (CONFIG_SYS_IMMR + 0x00560000)
  23 #define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
  24 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
  25 #define CONFIG_SYS_FSL_RST_ADDR                 (CONFIG_SYS_IMMR + 0x00ee00b0)
  26 #define CONFIG_SYS_FSL_SCFG_ADDR                (CONFIG_SYS_IMMR + 0x00570000)
  27 #define CONFIG_SYS_FSL_FMAN_ADDR                (CONFIG_SYS_IMMR + 0x00a00000)
  28 #define CONFIG_SYS_FSL_SERDES_ADDR              (CONFIG_SYS_IMMR + 0x00ea0000)
  29 #define CONFIG_SYS_FSL_DCFG_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
  30 #define CONFIG_SYS_FSL_CLK_ADDR                 (CONFIG_SYS_IMMR + 0x00ee1000)
  31 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011c0500)
  32 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011c0600)
  33 #define CONFIG_SYS_NS16550_COM3                 (CONFIG_SYS_IMMR + 0x011d0500)
  34 #define CONFIG_SYS_NS16550_COM4                 (CONFIG_SYS_IMMR + 0x011d0600)
  35 #define CONFIG_SYS_XHCI_USB1_ADDR               (CONFIG_SYS_IMMR + 0x01f00000)
  36 #define CONFIG_SYS_XHCI_USB2_ADDR               (CONFIG_SYS_IMMR + 0x02000000)
  37 #define CONFIG_SYS_XHCI_USB3_ADDR               (CONFIG_SYS_IMMR + 0x02100000)
  38 #define CONFIG_SYS_PCIE1_ADDR                   (CONFIG_SYS_IMMR + 0x2400000)
  39 #define CONFIG_SYS_PCIE2_ADDR                   (CONFIG_SYS_IMMR + 0x2500000)
  40 #define CONFIG_SYS_PCIE3_ADDR                   (CONFIG_SYS_IMMR + 0x2600000)
  41 #define CONFIG_SYS_SEC_MON_ADDR                 (CONFIG_SYS_IMMR + 0xe90000)
  42 #define CONFIG_SYS_SFP_ADDR                     (CONFIG_SYS_IMMR + 0xe80200)
  43
  44 #define CONFIG_SYS_FSL_TIMER_ADDR               0x02b00000
  45
  46 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01180000)
  47 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01190000)
  48 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011a0000)
  49 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011b0000)
  50
  51 #define WDOG1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01ad0000)
  52
  53 #define QSPI0_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x00550000)
  54 #define DSPI1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01100000)
  55
  56 #define LPUART_BASE                             (CONFIG_SYS_IMMR + 0x01950000)
  57
  58 #define AHCI_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x02200000)
  59
  60 #define CONFIG_SYS_PCIE1_PHYS_ADDR              0x4000000000ULL
  61 #define CONFIG_SYS_PCIE2_PHYS_ADDR              0x4800000000ULL
  62 #define CONFIG_SYS_PCIE3_PHYS_ADDR              0x5000000000ULL
  63 /* LUT registers */
  64 #ifdef CONFIG_ARCH_LS1012A
  65 #define PCIE_LUT_BASE                           0xC0000
  66 #else
  67 #define PCIE_LUT_BASE                           0x10000
  68 #endif
  69 #define PCIE_LUT_LCTRL0                         0x7F8
  70 #define PCIE_LUT_DBG                            0x7FC
  71
  72 /* TZ Address Space Controller Definitions */
  73 #define TZASC1_BASE                     0x01100000      /* as per CCSR map. */
  74 #define TZASC2_BASE                     0x01110000      /* as per CCSR map. */
  75 #define TZASC3_BASE                     0x01120000      /* as per CCSR map. */
  76 #define TZASC4_BASE                     0x01130000      /* as per CCSR map. */
  77 #define TZASC_BUILD_CONFIG_REG(x)       ((TZASC1_BASE + (x * 0x10000)))
  78 #define TZASC_ACTION_REG(x)             ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  79 #define TZASC_GATE_KEEPER(x)            ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  80 #define TZASC_REGION_BASE_LOW_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  81 #define TZASC_REGION_BASE_HIGH_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  82 #define TZASC_REGION_TOP_LOW_0(x)       ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  83 #define TZASC_REGION_TOP_HIGH_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  84 #define TZASC_REGION_ATTRIBUTES_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  85 #define TZASC_REGION_ID_ACCESS_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  86
  87 #define TP_ITYP_AV              0x00000001      /* Initiator available */
  88 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
  89 #define TP_ITYP_TYPE_ARM        0x0
  90 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
  91 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
  92 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
  93 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
  94 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
  95 #define TY_ITYP_VER_A7          0x1
  96 #define TY_ITYP_VER_A53         0x2
  97 #define TY_ITYP_VER_A57         0x3
  98 #define TY_ITYP_VER_A72         0x4
  99
 100 #define TP_CLUSTER_EOC          0xc0000000      /* end of clusters */
 101 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 102 #define TP_INIT_PER_CLUSTER     4
 103
 104 /*
 105  * Define default values for some CCSR macros to make header files cleaner*
 106  *
 107  * To completely disable CCSR relocation in a board header file, define
 108  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
 109  * to a value that is the same as CONFIG_SYS_CCSRBAR.
 110  */
 111
 112 #ifdef CONFIG_SYS_CCSRBAR_PHYS
 113 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
 114 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 115 #endif
 116
 117 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 118 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
 119 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
 120 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
 121 #endif
 122
 123 #ifndef CONFIG_SYS_CCSRBAR
 124 #define CONFIG_SYS_CCSRBAR              0x01000000
 125 #endif
 126
 127 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
 128 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
 129 #endif
 130
 131 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
 132 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     0x01000000
 133 #endif
 134
 135 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
 136                                  CONFIG_SYS_CCSRBAR_PHYS_LOW)
 137
 138 struct sys_info {
 139         unsigned long freq_processor[CONFIG_MAX_CPUS];
 140         /* frequency of platform PLL */
 141         unsigned long freq_systembus;
 142         unsigned long freq_ddrbus;
 143         unsigned long freq_localbus;
 144         unsigned long freq_sdhc;
 145 #ifdef CONFIG_SYS_DPAA_FMAN
 146         unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
 147 #endif
 148         unsigned long freq_qman;
 149 };
 150
 151 #define CONFIG_SYS_FSL_FM1_OFFSET               0xa00000
 152 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET        0xa88000
 153 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET        0xa89000
 154 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET        0xa8a000
 155 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET        0xa8b000
 156 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET        0xa8c000
 157 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET        0xa8d000
 158
 159 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET        0xae0000
 160 #define CONFIG_SYS_FSL_FM1_ADDR                 \
 161                 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
 162 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR          \
 163                 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 164
 165 #define CONFIG_SYS_FSL_SEC_OFFSET               0x700000ull
 166 #define CONFIG_SYS_FSL_JR0_OFFSET               0x710000ull
 167 #define CONFIG_SYS_FSL_SEC_ADDR \
 168         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 169 #define CONFIG_SYS_FSL_JR0_ADDR \
 170         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 171
 172 /* Device Configuration and Pin Control */
 173 #define DCFG_DCSR_PORCR1                0x0
 174
 175 struct ccsr_gur {
 176         u32     porsr1;         /* POR status 1 */
 177 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK       0xFF800000
 178         u32     porsr2;         /* POR status 2 */
 179         u8      res_008[0x20-0x8];
 180         u32     gpporcr1;       /* General-purpose POR configuration */
 181         u32     gpporcr2;
 182 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT      25
 183 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK       0x1F
 184 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT   20
 185 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK    0x1F
 186         u32     dcfg_fusesr;    /* Fuse status register */
 187         u8      res_02c[0x70-0x2c];
 188         u32     devdisr;        /* Device disable control */
 189 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1  0x80000000
 190 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2  0x40000000
 191 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3  0x20000000
 192 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4  0x10000000
 193 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5  0x08000000
 194 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6  0x04000000
 195 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9  0x00800000
 196 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
 197 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1  0x00800000
 198 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2  0x00400000
 199 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3  0x80000000
 200 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4  0x40000000
 201         u32     devdisr2;       /* Device disable control 2 */
 202         u32     devdisr3;       /* Device disable control 3 */
 203         u32     devdisr4;       /* Device disable control 4 */
 204         u32     devdisr5;       /* Device disable control 5 */
 205         u32     devdisr6;       /* Device disable control 6 */
 206         u32     devdisr7;       /* Device disable control 7 */
 207         u8      res_08c[0x94-0x8c];
 208         u32     coredisru;      /* uppper portion for support of 64 cores */
 209         u32     coredisrl;      /* lower portion for support of 64 cores */
 210         u8      res_09c[0xa0-0x9c];
 211         u32     pvr;            /* Processor version */
 212         u32     svr;            /* System version */
 213         u32     mvr;            /* Manufacturing version */
 214         u8      res_0ac[0xb0-0xac];
 215         u32     rstcr;          /* Reset control */
 216         u32     rstrqpblsr;     /* Reset request preboot loader status */
 217         u8      res_0b8[0xc0-0xb8];
 218         u32     rstrqmr1;       /* Reset request mask */
 219         u8      res_0c4[0xc8-0xc4];
 220         u32     rstrqsr1;       /* Reset request status */
 221         u8      res_0cc[0xd4-0xcc];
 222         u32     rstrqwdtmrl;    /* Reset request WDT mask */
 223         u8      res_0d8[0xdc-0xd8];
 224         u32     rstrqwdtsrl;    /* Reset request WDT status */
 225         u8      res_0e0[0xe4-0xe0];
 226         u32     brrl;           /* Boot release */
 227         u8      res_0e8[0x100-0xe8];
 228         u32     rcwsr[16];      /* Reset control word status */
 229 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT   25
 230 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK    0x1f
 231 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT   16
 232 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK    0x3f
 233 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK    0xffff0000
 234 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT   16
 235 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK    0x0000ffff
 236 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT   0
 237 #define RCW_SB_EN_REG_INDEX     7
 238 #define RCW_SB_EN_MASK          0x00200000
 239
 240         u8      res_140[0x200-0x140];
 241         u32     scratchrw[4];  /* Scratch Read/Write */
 242         u8      res_210[0x300-0x210];
 243         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 244         u8      res_310[0x400-0x310];
 245         u32     crstsr[12];
 246         u8      res_430[0x500-0x430];
 247
 248         /* PCI Express n Logical I/O Device Number register */
 249         u32 dcfg_ccsr_pex1liodnr;
 250         u32 dcfg_ccsr_pex2liodnr;
 251         u32 dcfg_ccsr_pex3liodnr;
 252         u32 dcfg_ccsr_pex4liodnr;
 253         /* RIO n Logical I/O Device Number register */
 254         u32 dcfg_ccsr_rio1liodnr;
 255         u32 dcfg_ccsr_rio2liodnr;
 256         u32 dcfg_ccsr_rio3liodnr;
 257         u32 dcfg_ccsr_rio4liodnr;
 258         /* USB Logical I/O Device Number register */
 259         u32 dcfg_ccsr_usb1liodnr;
 260         u32 dcfg_ccsr_usb2liodnr;
 261         u32 dcfg_ccsr_usb3liodnr;
 262         u32 dcfg_ccsr_usb4liodnr;
 263         /* SD/MMC Logical I/O Device Number register */
 264         u32 dcfg_ccsr_sdmmc1liodnr;
 265         u32 dcfg_ccsr_sdmmc2liodnr;
 266         u32 dcfg_ccsr_sdmmc3liodnr;
 267         u32 dcfg_ccsr_sdmmc4liodnr;
 268         /* RIO Message Unit Logical I/O Device Number register */
 269         u32 dcfg_ccsr_riomaintliodnr;
 270
 271         u8      res_544[0x550-0x544];
 272         u32     sataliodnr[4];
 273         u8      res_560[0x570-0x560];
 274
 275         u32 dcfg_ccsr_misc1liodnr;
 276         u32 dcfg_ccsr_misc2liodnr;
 277         u32 dcfg_ccsr_misc3liodnr;
 278         u32 dcfg_ccsr_misc4liodnr;
 279         u32 dcfg_ccsr_dma1liodnr;
 280         u32 dcfg_ccsr_dma2liodnr;
 281         u32 dcfg_ccsr_dma3liodnr;
 282         u32 dcfg_ccsr_dma4liodnr;
 283         u32 dcfg_ccsr_spare1liodnr;
 284         u32 dcfg_ccsr_spare2liodnr;
 285         u32 dcfg_ccsr_spare3liodnr;
 286         u32 dcfg_ccsr_spare4liodnr;
 287         u8      res_5a0[0x600-0x5a0];
 288         u32 dcfg_ccsr_pblsr;
 289
 290         u32     pamubypenr;
 291         u32     dmacr1;
 292
 293         u8      res_60c[0x610-0x60c];
 294         u32 dcfg_ccsr_gensr1;
 295         u32 dcfg_ccsr_gensr2;
 296         u32 dcfg_ccsr_gensr3;
 297         u32 dcfg_ccsr_gensr4;
 298         u32 dcfg_ccsr_gencr1;
 299         u32 dcfg_ccsr_gencr2;
 300         u32 dcfg_ccsr_gencr3;
 301         u32 dcfg_ccsr_gencr4;
 302         u32 dcfg_ccsr_gencr5;
 303         u32 dcfg_ccsr_gencr6;
 304         u32 dcfg_ccsr_gencr7;
 305         u8      res_63c[0x658-0x63c];
 306         u32 dcfg_ccsr_cgensr1;
 307         u32 dcfg_ccsr_cgensr0;
 308         u8      res_660[0x678-0x660];
 309         u32 dcfg_ccsr_cgencr1;
 310
 311         u32 dcfg_ccsr_cgencr0;
 312         u8      res_680[0x700-0x680];
 313         u32 dcfg_ccsr_sriopstecr;
 314         u32 dcfg_ccsr_dcsrcr;
 315
 316         u8      res_708[0x740-0x708];   /* add more registers when needed */
 317         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 318         struct {
 319                 u32     upper;
 320                 u32     lower;
 321         } tp_cluster[16];
 322         u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
 323         u32 dcfg_ccsr_qmbm_warmrst;
 324         u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
 325         u32 dcfg_ccsr_reserved0;
 326         u32 dcfg_ccsr_reserved1;
 327 };
 328
 329 #define SCFG_QSPI_CLKSEL                0x40100000
 330 #define SCFG_USBDRVVBUS_SELCR_USB1      0x00000000
 331 #define SCFG_USBDRVVBUS_SELCR_USB2      0x00000001
 332 #define SCFG_USBDRVVBUS_SELCR_USB3      0x00000002
 333 #define SCFG_USBPWRFAULT_INACTIVE       0x00000000
 334 #define SCFG_USBPWRFAULT_SHARED         0x00000001
 335 #define SCFG_USBPWRFAULT_DEDICATED      0x00000002
 336 #define SCFG_USBPWRFAULT_USB3_SHIFT     4
 337 #define SCFG_USBPWRFAULT_USB2_SHIFT     2
 338 #define SCFG_USBPWRFAULT_USB1_SHIFT     0
 339
 340 #define SCFG_SNPCNFGCR_SECRDSNP         0x80000000
 341 #define SCFG_SNPCNFGCR_SECWRSNP         0x40000000
 342 #define SCFG_SNPCNFGCR_SATARDSNP        0x00800000
 343 #define SCFG_SNPCNFGCR_SATAWRSNP        0x00400000
 344
 345 /* Supplemental Configuration Unit */
 346 struct ccsr_scfg {
 347         u8 res_000[0x100-0x000];
 348         u32 usb2_icid;
 349         u32 usb3_icid;
 350         u8 res_108[0x114-0x108];
 351         u32 dma_icid;
 352         u32 sata_icid;
 353         u32 usb1_icid;
 354         u32 qe_icid;
 355         u32 sdhc_icid;
 356         u32 edma_icid;
 357         u32 etr_icid;
 358         u32 core_sft_rst[4];
 359         u8 res_140[0x158-0x140];
 360         u32 altcbar;
 361         u32 qspi_cfg;
 362         u8 res_160[0x180-0x160];
 363         u32 dmamcr;
 364         u8 res_184[0x18c-0x184];
 365         u32 debug_icid;
 366         u8 res_190[0x1a4-0x190];
 367         u32 snpcnfgcr;
 368         u8 res_1a8[0x1ac-0x1a8];
 369         u32 intpcr;
 370         u8 res_1b0[0x204-0x1b0];
 371         u32 coresrencr;
 372         u8 res_208[0x220-0x208];
 373         u32 rvbar0_0;
 374         u32 rvbar0_1;
 375         u32 rvbar1_0;
 376         u32 rvbar1_1;
 377         u32 rvbar2_0;
 378         u32 rvbar2_1;
 379         u32 rvbar3_0;
 380         u32 rvbar3_1;
 381         u32 lpmcsr;
 382         u8 res_244[0x400-0x244];
 383         u32 qspidqscr;
 384         u32 ecgtxcmcr;
 385         u32 sdhciovselcr;
 386         u32 rcwpmuxcr0;
 387         u32 usbdrvvbus_selcr;
 388         u32 usbpwrfault_selcr;
 389         u32 usb_refclk_selcr1;
 390         u32 usb_refclk_selcr2;
 391         u32 usb_refclk_selcr3;
 392         u8 res_424[0x600-0x424];
 393         u32 scratchrw[4];
 394         u8 res_610[0x680-0x610];
 395         u32 corebcr;
 396         u8 res_684[0x1000-0x684];
 397         u32 pex1msiir;
 398         u32 pex1msir;
 399         u8 res_1008[0x2000-0x1008];
 400         u32 pex2;
 401         u32 pex2msir;
 402         u8 res_2008[0x3000-0x2008];
 403         u32 pex3msiir;
 404         u32 pex3msir;
 405 };
 406
 407 /* Clocking */
 408 struct ccsr_clk {
 409         struct {
 410                 u32 clkcncsr;   /* core cluster n clock control status */
 411                 u8  res_004[0x0c];
 412                 u32 clkcghwacsr; /* Clock generator n hardware accelerator */
 413                 u8  res_014[0x0c];
 414         } clkcsr[4];
 415         u8      res_040[0x780]; /* 0x100 */
 416         struct {
 417                 u32 pllcngsr;
 418                 u8 res_804[0x1c];
 419         } pllcgsr[2];
 420         u8      res_840[0x1c0];
 421         u32     clkpcsr;        /* 0xa00 Platform clock domain control/status */
 422         u8      res_a04[0x1fc];
 423         u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
 424         u8      res_c04[0x1c];
 425         u32     plldgsr;        /* 0xc20 DDR PLL General Status */
 426         u8      res_c24[0x3dc];
 427 };
 428
 429 /* System Counter */
 430 struct sctr_regs {
 431         u32 cntcr;
 432         u32 cntsr;
 433         u32 cntcv1;
 434         u32 cntcv2;
 435         u32 resv1[4];
 436         u32 cntfid0;
 437         u32 cntfid1;
 438         u32 resv2[1002];
 439         u32 counterid[12];
 440 };
 441
 442 #define SRDS_MAX_LANES          4
 443 struct ccsr_serdes {
 444         struct {
 445                 u32     rstctl; /* Reset Control Register */
 446 #define SRDS_RSTCTL_RST         0x80000000
 447 #define SRDS_RSTCTL_RSTDONE     0x40000000
 448 #define SRDS_RSTCTL_RSTERR      0x20000000
 449 #define SRDS_RSTCTL_SWRST       0x10000000
 450 #define SRDS_RSTCTL_SDEN        0x00000020
 451 #define SRDS_RSTCTL_SDRST_B     0x00000040
 452 #define SRDS_RSTCTL_PLLRST_B    0x00000080
 453                 u32     pllcr0; /* PLL Control Register 0 */
 454 #define SRDS_PLLCR0_POFF                0x80000000
 455 #define SRDS_PLLCR0_RFCK_SEL_MASK       0x70000000
 456 #define SRDS_PLLCR0_RFCK_SEL_100        0x00000000
 457 #define SRDS_PLLCR0_RFCK_SEL_125        0x10000000
 458 #define SRDS_PLLCR0_RFCK_SEL_156_25     0x20000000
 459 #define SRDS_PLLCR0_RFCK_SEL_150        0x30000000
 460 #define SRDS_PLLCR0_RFCK_SEL_161_13     0x40000000
 461 #define SRDS_PLLCR0_RFCK_SEL_122_88     0x50000000
 462 #define SRDS_PLLCR0_PLL_LCK             0x00800000
 463 #define SRDS_PLLCR0_FRATE_SEL_MASK      0x000f0000
 464 #define SRDS_PLLCR0_FRATE_SEL_5         0x00000000
 465 #define SRDS_PLLCR0_FRATE_SEL_3_75      0x00050000
 466 #define SRDS_PLLCR0_FRATE_SEL_5_15      0x00060000
 467 #define SRDS_PLLCR0_FRATE_SEL_4         0x00070000
 468 #define SRDS_PLLCR0_FRATE_SEL_3_12      0x00090000
 469 #define SRDS_PLLCR0_FRATE_SEL_3         0x000a0000
 470                 u32     pllcr1; /* PLL Control Register 1 */
 471 #define SRDS_PLLCR1_PLL_BWSEL   0x08000000
 472                 u32     res_0c; /* 0x00c */
 473                 u32     pllcr3;
 474                 u32     pllcr4;
 475                 u32     pllcr5; /* 0x018 SerDes PLL1 Control 5 */
 476                 u8      res_1c[0x20-0x1c];
 477         } bank[2];
 478         u8      res_40[0x90-0x40];
 479         u32     srdstcalcr;     /* 0x90 TX Calibration Control */
 480         u8      res_94[0xa0-0x94];
 481         u32     srdsrcalcr;     /* 0xa0 RX Calibration Control */
 482         u8      res_a4[0xb0-0xa4];
 483         u32     srdsgr0;        /* 0xb0 General Register 0 */
 484         u8      res_b4[0x100-0xb4];
 485         struct {
 486                 u32     lnpssr0;        /* 0x100, 0x120, 0x140, 0x160 */
 487                 u8      res_104[0x120-0x104];
 488         } lnpssr[4];    /* Lane A, B, C, D */
 489         u8      res_180[0x200-0x180];
 490         u32     srdspccr0;      /* 0x200 Protocol Configuration 0 */
 491         u32     srdspccr1;      /* 0x204 Protocol Configuration 1 */
 492         u32     srdspccr2;      /* 0x208 Protocol Configuration 2 */
 493         u32     srdspccr3;      /* 0x20c Protocol Configuration 3 */
 494         u32     srdspccr4;      /* 0x210 Protocol Configuration 4 */
 495         u32     srdspccr5;      /* 0x214 Protocol Configuration 5 */
 496         u32     srdspccr6;      /* 0x218 Protocol Configuration 6 */
 497         u32     srdspccr7;      /* 0x21c Protocol Configuration 7 */
 498         u32     srdspccr8;      /* 0x220 Protocol Configuration 8 */
 499         u32     srdspccr9;      /* 0x224 Protocol Configuration 9 */
 500         u32     srdspccra;      /* 0x228 Protocol Configuration A */
 501         u32     srdspccrb;      /* 0x22c Protocol Configuration B */
 502         u8      res_230[0x800-0x230];
 503         struct {
 504                 u32     gcr0;   /* 0x800 General Control Register 0 */
 505                 u32     gcr1;   /* 0x804 General Control Register 1 */
 506                 u32     gcr2;   /* 0x808 General Control Register 2 */
 507                 u32     sscr0;
 508                 u32     recr0;  /* 0x810 Receive Equalization Control */
 509                 u32     recr1;
 510                 u32     tecr0;  /* 0x818 Transmit Equalization Control */
 511                 u32     sscr1;
 512                 u32     ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
 513                 u8      res_824[0x83c-0x824];
 514                 u32     tcsr3;
 515         } lane[4];      /* Lane A, B, C, D */
 516         u8      res_900[0x1000-0x900];  /* from 0x900 to 0xfff */
 517         struct {
 518                 u32     srdspexcr0;     /* 0x1000, 0x1040, 0x1080 */
 519                 u8      res_1004[0x1040-0x1004];
 520         } pcie[3];
 521         u8      res_10c0[0x1800-0x10c0];
 522         struct {
 523                 u8      res_1800[0x1804-0x1800];
 524                 u32     srdssgmiicr1;   /* 0x1804 SGMII Protocol Control 1 */
 525                 u8      res_1808[0x180c-0x1808];
 526                 u32     srdssgmiicr3;   /* 0x180c SGMII Protocol Control 3 */
 527         } sgmii[4];     /* Lane A, B, C, D */
 528         u8      res_1840[0x1880-0x1840];
 529         struct {
 530                 u8      res_1880[0x1884-0x1880];
 531                 u32     srdsqsgmiicr1;  /* 0x1884 QSGMII Protocol Control 1 */
 532                 u8      res_1888[0x188c-0x1888];
 533                 u32     srdsqsgmiicr3;  /* 0x188c QSGMII Protocol Control 3 */
 534         } qsgmii[2];    /* Lane A, B */
 535         u8      res_18a0[0x1980-0x18a0];
 536         struct {
 537                 u8      res_1980[0x1984-0x1980];
 538                 u32     srdsxficr1;     /* 0x1984 XFI Protocol Control 1 */
 539                 u8      res_1988[0x198c-0x1988];
 540                 u32     srdsxficr3;     /* 0x198c XFI Protocol Control 3 */
 541         } xfi[2];       /* Lane A, B */
 542         u8      res_19a0[0x2000-0x19a0];        /* from 0x19a0 to 0x1fff */
 543 };
 544
 545 #define CCI400_CTRLORD_TERM_BARRIER     0x00000008
 546 #define CCI400_CTRLORD_EN_BARRIER       0
 547 #define CCI400_SHAORD_NON_SHAREABLE     0x00000002
 548 #define CCI400_DVM_MESSAGE_REQ_EN       0x00000002
 549 #define CCI400_SNOOP_REQ_EN             0x00000001
 550
 551 /* CCI-400 registers */
 552 struct ccsr_cci400 {
 553         u32 ctrl_ord;                   /* Control Override */
 554         u32 spec_ctrl;                  /* Speculation Control */
 555         u32 secure_access;              /* Secure Access */
 556         u32 status;                     /* Status */
 557         u32 impr_err;                   /* Imprecise Error */
 558         u8 res_14[0x100 - 0x14];
 559         u32 pmcr;                       /* Performance Monitor Control */
 560         u8 res_104[0xfd0 - 0x104];
 561         u32 pid[8];                     /* Peripheral ID */
 562         u32 cid[4];                     /* Component ID */
 563         struct {
 564                 u32 snoop_ctrl;         /* Snoop Control */
 565                 u32 sha_ord;            /* Shareable Override */
 566                 u8 res_1008[0x1100 - 0x1008];
 567                 u32 rc_qos_ord;         /* read channel QoS Value Override */
 568                 u32 wc_qos_ord;         /* read channel QoS Value Override */
 569                 u8 res_1108[0x110c - 0x1108];
 570                 u32 qos_ctrl;           /* QoS Control */
 571                 u32 max_ot;             /* Max OT */
 572                 u8 res_1114[0x1130 - 0x1114];
 573                 u32 target_lat;         /* Target Latency */
 574                 u32 latency_regu;       /* Latency Regulation */
 575                 u32 qos_range;          /* QoS Range */
 576                 u8 res_113c[0x2000 - 0x113c];
 577         } slave[5];                     /* Slave Interface */
 578         u8 res_6000[0x9004 - 0x6000];
 579         u32 cycle_counter;              /* Cycle counter */
 580         u32 count_ctrl;                 /* Count Control */
 581         u32 overflow_status;            /* Overflow Flag Status */
 582         u8 res_9010[0xa000 - 0x9010];
 583         struct {
 584                 u32 event_select;       /* Event Select */
 585                 u32 event_count;        /* Event Count */
 586                 u32 counter_ctrl;       /* Counter Control */
 587                 u32 overflow_status;    /* Overflow Flag Status */
 588                 u8 res_a010[0xb000 - 0xa010];
 589         } pcounter[4];                  /* Performance Counter */
 590         u8 res_e004[0x10000 - 0xe004];
 591 };
 592
 593 /* MMU 500 */
 594 #define SMMU_SCR0                       (SMMU_BASE + 0x0)
 595 #define SMMU_SCR1                       (SMMU_BASE + 0x4)
 596 #define SMMU_SCR2                       (SMMU_BASE + 0x8)
 597 #define SMMU_SACR                       (SMMU_BASE + 0x10)
 598 #define SMMU_IDR0                       (SMMU_BASE + 0x20)
 599 #define SMMU_IDR1                       (SMMU_BASE + 0x24)
 600
 601 #define SMMU_NSCR0                      (SMMU_BASE + 0x400)
 602 #define SMMU_NSCR2                      (SMMU_BASE + 0x408)
 603 #define SMMU_NSACR                      (SMMU_BASE + 0x410)
 604
 605 #define SCR0_CLIENTPD_MASK              0x00000001
 606 #define SCR0_USFCFG_MASK                0x00000400
 607
 608 uint get_svr(void);
 609
 610 #endif  /* __ARCH_FSL_LSCH2_IMMAP_H__*/