arch/arm/include/asm/arch-am33xx/hardware_am43xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * hardware_am43xx.h
   4  *
   5  * AM43xx hardware specific header
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #ifndef __AM43XX_HARDWARE_AM43XX_H
  11 #define __AM43XX_HARDWARE_AM43XX_H
  12
  13 #ifndef __ASSEMBLY__
  14 #include <linux/bitops.h>
  15 #endif
  16
  17 /* Module base addresses */
  18
  19 /* L3 Fast Configuration Bandwidth Limiter Base Address */
  20 #define L3F_CFG_BWLIMITER               0x44005200
  21
  22 /* UART Base Address */
  23 #define UART0_BASE                      0x44E09000
  24
  25 /* GPIO Base address */
  26 #define GPIO2_BASE                      0x481AC000
  27
  28 /* Watchdog Timer */
  29 #define WDT_BASE                        0x44E35000
  30
  31 /* Control Module Base Address */
  32 #define CTRL_BASE                       0x44E10000
  33 #define CTRL_DEVICE_BASE                0x44E10600
  34
  35 /* PRCM Base Address */
  36 #define PRCM_BASE                       0x44DF0000
  37 #define CM_WKUP                         0x44DF2800
  38 #define CM_PER                          0x44DF8800
  39 #define CM_DPLL                         0x44DF4200
  40 #define CM_RTC                          0x44DF8500
  41
  42 #define PRM_RSTCTRL                     (PRCM_BASE + 0x4000)
  43 #define PRM_RSTST                       (PRM_RSTCTRL + 4)
  44
  45 /* VTP Base address */
  46 #define VTP0_CTRL_ADDR                  0x44E10E0C
  47 #define VTP1_CTRL_ADDR                  0x48140E10
  48
  49 /* USB CTRL Base Address */
  50 #define USB1_CTRL                       0x44e10628
  51 #define USB1_CTRL_CM_PWRDN              BIT(0)
  52 #define USB1_CTRL_OTG_PWRDN             BIT(1)
  53
  54 /* DDR Base address */
  55 #define DDR_PHY_CMD_ADDR                0x44E12000
  56 #define DDR_PHY_DATA_ADDR               0x44E120C8
  57 #define DDR_PHY_CMD_ADDR2               0x47C0C800
  58 #define DDR_PHY_DATA_ADDR2              0x47C0C8C8
  59 #define DDR_DATA_REGS_NR                2
  60
  61 /* CPSW Config space */
  62 #define CPSW_MDIO_BASE                  0x4A101000
  63
  64 /* RTC base address */
  65 #define RTC_BASE                        0x44E3E000
  66
  67 /* USB OTG */
  68 #define USB_OTG_SS1_BASE                0x48390000
  69 #define USB_OTG_SS1_GLUE_BASE           0x48380000
  70 #define USB2_PHY1_POWER                 0x44E10620
  71
  72 #define USB_OTG_SS2_BASE                0x483D0000
  73 #define USB_OTG_SS2_GLUE_BASE           0x483C0000
  74 #define USB2_PHY2_POWER                 0x44E10628
  75
  76 /* USB Clock Control */
  77 #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
  78 #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
  79 #define USBOTGSSX_CLKCTRL_MODULE_EN     (1 << 1)
  80 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
  81
  82 #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
  83 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
  84 #define USBPHYOCPSCP_MODULE_EN  (1 << 1)
  85 #define CM_DEVICE_INST                  0x44df4100
  86 #define PRM_DEVICE_INST                 0x44df4000
  87
  88 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960   (1 << 8)
  89 #define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K        (1 << 8)
  90
  91 /* EDMA3 Base Address */
  92 #define EDMA3_BASE                              0x49000000
  93
  94 #endif /* __AM43XX_HARDWARE_AM43XX_H */