arch/arm/dts/zynqmp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP
   4  *
   5  * (C) Copyright 2014 - 2020, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
  16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
  17
  18 / {
  19         compatible = "xlnx,zynqmp";
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@0 {
  28                         compatible = "arm,cortex-a53";
  29                         device_type = "cpu";
  30                         enable-method = "psci";
  31                         operating-points-v2 = <&cpu_opp_table>;
  32                         reg = <0x0>;
  33                         cpu-idle-states = <&CPU_SLEEP_0>;
  34                 };
  35
  36                 cpu1: cpu@1 {
  37                         compatible = "arm,cortex-a53";
  38                         device_type = "cpu";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                         operating-points-v2 = <&cpu_opp_table>;
  42                         cpu-idle-states = <&CPU_SLEEP_0>;
  43                 };
  44
  45                 cpu2: cpu@2 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         enable-method = "psci";
  49                         reg = <0x2>;
  50                         operating-points-v2 = <&cpu_opp_table>;
  51                         cpu-idle-states = <&CPU_SLEEP_0>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         compatible = "arm,cortex-a53";
  56                         device_type = "cpu";
  57                         enable-method = "psci";
  58                         reg = <0x3>;
  59                         operating-points-v2 = <&cpu_opp_table>;
  60                         cpu-idle-states = <&CPU_SLEEP_0>;
  61                 };
  62
  63                 idle-states {
  64                         entry-method = "psci";
  65
  66                         CPU_SLEEP_0: cpu-sleep-0 {
  67                                 compatible = "arm,idle-state";
  68                                 arm,psci-suspend-param = <0x40000000>;
  69                                 local-timer-stop;
  70                                 entry-latency-us = <300>;
  71                                 exit-latency-us = <600>;
  72                                 min-residency-us = <10000>;
  73                         };
  74                 };
  75         };
  76
  77         cpu_opp_table: cpu-opp-table {
  78                 compatible = "operating-points-v2";
  79                 opp-shared;
  80                 opp00 {
  81                         opp-hz = /bits/ 64 <1199999988>;
  82                         opp-microvolt = <1000000>;
  83                         clock-latency-ns = <500000>;
  84                 };
  85                 opp01 {
  86                         opp-hz = /bits/ 64 <599999994>;
  87                         opp-microvolt = <1000000>;
  88                         clock-latency-ns = <500000>;
  89                 };
  90                 opp02 {
  91                         opp-hz = /bits/ 64 <399999996>;
  92                         opp-microvolt = <1000000>;
  93                         clock-latency-ns = <500000>;
  94                 };
  95                 opp03 {
  96                         opp-hz = /bits/ 64 <299999997>;
  97                         opp-microvolt = <1000000>;
  98                         clock-latency-ns = <500000>;
  99                 };
 100         };
 101
 102         zynqmp_ipi {
 103                 u-boot,dm-pre-reloc;
 104                 compatible = "xlnx,zynqmp-ipi-mailbox";
 105                 interrupt-parent = <&gic>;
 106                 interrupts = <0 35 4>;
 107                 xlnx,ipi-id = <0>;
 108                 #address-cells = <2>;
 109                 #size-cells = <2>;
 110                 ranges;
 111
 112                 ipi_mailbox_pmu1: mailbox@ff990400 {
 113                         u-boot,dm-pre-reloc;
 114                         reg = <0x0 0xff9905c0 0x0 0x20>,
 115                               <0x0 0xff9905e0 0x0 0x20>,
 116                               <0x0 0xff990e80 0x0 0x20>,
 117                               <0x0 0xff990ea0 0x0 0x20>;
 118                         reg-names = "local_request_region", "local_response_region",
 119                                     "remote_request_region", "remote_response_region";
 120                         #mbox-cells = <1>;
 121                         xlnx,ipi-id = <4>;
 122                 };
 123         };
 124
 125         dcc: dcc {
 126                 compatible = "arm,dcc";
 127                 status = "disabled";
 128                 u-boot,dm-pre-reloc;
 129         };
 130
 131         pmu {
 132                 compatible = "arm,armv8-pmuv3";
 133                 interrupt-parent = <&gic>;
 134                 interrupts = <0 143 4>,
 135                              <0 144 4>,
 136                              <0 145 4>,
 137                              <0 146 4>;
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         firmware {
 146                 zynqmp_firmware: zynqmp-firmware {
 147                         compatible = "xlnx,zynqmp-firmware";
 148                         method = "smc";
 149                         #power-domain-cells = <0x1>;
 150                         u-boot,dm-pre-reloc;
 151
 152                         zynqmp_pcap: pcap {
 153                                 compatible = "xlnx,zynqmp-pcap-fpga";
 154                                 clock-names = "ref_clk";
 155                         };
 156
 157                         zynqmp_power: zynqmp-power {
 158                                 u-boot,dm-pre-reloc;
 159                                 compatible = "xlnx,zynqmp-power";
 160                                 interrupt-parent = <&gic>;
 161                                 interrupts = <0 35 4>;
 162                                 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
 163                                 mbox-names = "tx", "rx";
 164                         };
 165
 166                         zynqmp_reset: reset-controller {
 167                                 compatible = "xlnx,zynqmp-reset";
 168                                 #reset-cells = <1>;
 169                         };
 170                 };
 171         };
 172
 173         timer {
 174                 compatible = "arm,armv8-timer";
 175                 interrupt-parent = <&gic>;
 176                 interrupts = <1 13 0xf08>,
 177                              <1 14 0xf08>,
 178                              <1 11 0xf08>,
 179                              <1 10 0xf08>;
 180         };
 181
 182         edac {
 183                 compatible = "arm,cortex-a53-edac";
 184         };
 185
 186         fpga_full: fpga-full {
 187                 compatible = "fpga-region";
 188                 fpga-mgr = <&zynqmp_pcap>;
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 ranges;
 192         };
 193
 194         nvmem_firmware {
 195                 compatible = "xlnx,zynqmp-nvmem-fw";
 196                 #address-cells = <1>;
 197                 #size-cells = <1>;
 198
 199                 soc_revision: soc_revision@0 {
 200                         reg = <0x0 0x4>;
 201                 };
 202         };
 203
 204         amba_apu: amba-apu@0 {
 205                 compatible = "simple-bus";
 206                 #address-cells = <2>;
 207                 #size-cells = <1>;
 208                 ranges = <0 0 0 0 0xffffffff>;
 209
 210                 gic: interrupt-controller@f9010000 {
 211                         compatible = "arm,gic-400";
 212                         #interrupt-cells = <3>;
 213                         reg = <0x0 0xf9010000 0x10000>,
 214                               <0x0 0xf9020000 0x20000>,
 215                               <0x0 0xf9040000 0x20000>,
 216                               <0x0 0xf9060000 0x20000>;
 217                         interrupt-controller;
 218                         interrupt-parent = <&gic>;
 219                         interrupts = <1 9 0xf04>;
 220                 };
 221         };
 222
 223         amba: amba {
 224                 compatible = "simple-bus";
 225                 u-boot,dm-pre-reloc;
 226                 #address-cells = <2>;
 227                 #size-cells = <2>;
 228                 ranges;
 229
 230                 can0: can@ff060000 {
 231                         compatible = "xlnx,zynq-can-1.0";
 232                         status = "disabled";
 233                         clock-names = "can_clk", "pclk";
 234                         reg = <0x0 0xff060000 0x0 0x1000>;
 235                         interrupts = <0 23 4>;
 236                         interrupt-parent = <&gic>;
 237                         tx-fifo-depth = <0x40>;
 238                         rx-fifo-depth = <0x40>;
 239                         power-domains = <&zynqmp_firmware PD_CAN_0>;
 240                 };
 241
 242                 can1: can@ff070000 {
 243                         compatible = "xlnx,zynq-can-1.0";
 244                         status = "disabled";
 245                         clock-names = "can_clk", "pclk";
 246                         reg = <0x0 0xff070000 0x0 0x1000>;
 247                         interrupts = <0 24 4>;
 248                         interrupt-parent = <&gic>;
 249                         tx-fifo-depth = <0x40>;
 250                         rx-fifo-depth = <0x40>;
 251                         power-domains = <&zynqmp_firmware PD_CAN_1>;
 252                 };
 253
 254                 cci: cci@fd6e0000 {
 255                         compatible = "arm,cci-400";
 256                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 257                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 258                         #address-cells = <1>;
 259                         #size-cells = <1>;
 260
 261                         pmu@9000 {
 262                                 compatible = "arm,cci-400-pmu,r1";
 263                                 reg = <0x9000 0x5000>;
 264                                 interrupt-parent = <&gic>;
 265                                 interrupts = <0 123 4>,
 266                                              <0 123 4>,
 267                                              <0 123 4>,
 268                                              <0 123 4>,
 269                                              <0 123 4>;
 270                         };
 271                 };
 272
 273                 /* GDMA */
 274                 fpd_dma_chan1: dma@fd500000 {
 275                         status = "disabled";
 276                         compatible = "xlnx,zynqmp-dma-1.0";
 277                         reg = <0x0 0xfd500000 0x0 0x1000>;
 278                         interrupt-parent = <&gic>;
 279                         interrupts = <0 124 4>;
 280                         clock-names = "clk_main", "clk_apb";
 281                         xlnx,bus-width = <128>;
 282                         #stream-id-cells = <1>;
 283                         iommus = <&smmu 0x14e8>;
 284                         power-domains = <&zynqmp_firmware PD_GDMA>;
 285                 };
 286
 287                 fpd_dma_chan2: dma@fd510000 {
 288                         status = "disabled";
 289                         compatible = "xlnx,zynqmp-dma-1.0";
 290                         reg = <0x0 0xfd510000 0x0 0x1000>;
 291                         interrupt-parent = <&gic>;
 292                         interrupts = <0 125 4>;
 293                         clock-names = "clk_main", "clk_apb";
 294                         xlnx,bus-width = <128>;
 295                         #stream-id-cells = <1>;
 296                         iommus = <&smmu 0x14e9>;
 297                         power-domains = <&zynqmp_firmware PD_GDMA>;
 298                 };
 299
 300                 fpd_dma_chan3: dma@fd520000 {
 301                         status = "disabled";
 302                         compatible = "xlnx,zynqmp-dma-1.0";
 303                         reg = <0x0 0xfd520000 0x0 0x1000>;
 304                         interrupt-parent = <&gic>;
 305                         interrupts = <0 126 4>;
 306                         clock-names = "clk_main", "clk_apb";
 307                         xlnx,bus-width = <128>;
 308                         #stream-id-cells = <1>;
 309                         iommus = <&smmu 0x14ea>;
 310                         power-domains = <&zynqmp_firmware PD_GDMA>;
 311                 };
 312
 313                 fpd_dma_chan4: dma@fd530000 {
 314                         status = "disabled";
 315                         compatible = "xlnx,zynqmp-dma-1.0";
 316                         reg = <0x0 0xfd530000 0x0 0x1000>;
 317                         interrupt-parent = <&gic>;
 318                         interrupts = <0 127 4>;
 319                         clock-names = "clk_main", "clk_apb";
 320                         xlnx,bus-width = <128>;
 321                         #stream-id-cells = <1>;
 322                         iommus = <&smmu 0x14eb>;
 323                         power-domains = <&zynqmp_firmware PD_GDMA>;
 324                 };
 325
 326                 fpd_dma_chan5: dma@fd540000 {
 327                         status = "disabled";
 328                         compatible = "xlnx,zynqmp-dma-1.0";
 329                         reg = <0x0 0xfd540000 0x0 0x1000>;
 330                         interrupt-parent = <&gic>;
 331                         interrupts = <0 128 4>;
 332                         clock-names = "clk_main", "clk_apb";
 333                         xlnx,bus-width = <128>;
 334                         #stream-id-cells = <1>;
 335                         iommus = <&smmu 0x14ec>;
 336                         power-domains = <&zynqmp_firmware PD_GDMA>;
 337                 };
 338
 339                 fpd_dma_chan6: dma@fd550000 {
 340                         status = "disabled";
 341                         compatible = "xlnx,zynqmp-dma-1.0";
 342                         reg = <0x0 0xfd550000 0x0 0x1000>;
 343                         interrupt-parent = <&gic>;
 344                         interrupts = <0 129 4>;
 345                         clock-names = "clk_main", "clk_apb";
 346                         xlnx,bus-width = <128>;
 347                         #stream-id-cells = <1>;
 348                         iommus = <&smmu 0x14ed>;
 349                         power-domains = <&zynqmp_firmware PD_GDMA>;
 350                 };
 351
 352                 fpd_dma_chan7: dma@fd560000 {
 353                         status = "disabled";
 354                         compatible = "xlnx,zynqmp-dma-1.0";
 355                         reg = <0x0 0xfd560000 0x0 0x1000>;
 356                         interrupt-parent = <&gic>;
 357                         interrupts = <0 130 4>;
 358                         clock-names = "clk_main", "clk_apb";
 359                         xlnx,bus-width = <128>;
 360                         #stream-id-cells = <1>;
 361                         iommus = <&smmu 0x14ee>;
 362                         power-domains = <&zynqmp_firmware PD_GDMA>;
 363                 };
 364
 365                 fpd_dma_chan8: dma@fd570000 {
 366                         status = "disabled";
 367                         compatible = "xlnx,zynqmp-dma-1.0";
 368                         reg = <0x0 0xfd570000 0x0 0x1000>;
 369                         interrupt-parent = <&gic>;
 370                         interrupts = <0 131 4>;
 371                         clock-names = "clk_main", "clk_apb";
 372                         xlnx,bus-width = <128>;
 373                         #stream-id-cells = <1>;
 374                         iommus = <&smmu 0x14ef>;
 375                         power-domains = <&zynqmp_firmware PD_GDMA>;
 376                 };
 377
 378                 gpu: gpu@fd4b0000 {
 379                         status = "disabled";
 380                         compatible = "arm,mali-400", "arm,mali-utgard";
 381                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 382                         interrupt-parent = <&gic>;
 383                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 384                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 385                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 386                         power-domains = <&zynqmp_firmware PD_GPU>;
 387                 };
 388
 389                 /* LPDDMA default allows only secured access. inorder to enable
 390                  * These dma channels, Users should ensure that these dma
 391                  * Channels are allowed for non secure access.
 392                  */
 393                 lpd_dma_chan1: dma@ffa80000 {
 394                         status = "disabled";
 395                         compatible = "xlnx,zynqmp-dma-1.0";
 396                         reg = <0x0 0xffa80000 0x0 0x1000>;
 397                         interrupt-parent = <&gic>;
 398                         interrupts = <0 77 4>;
 399                         clock-names = "clk_main", "clk_apb";
 400                         xlnx,bus-width = <64>;
 401                         #stream-id-cells = <1>;
 402                         iommus = <&smmu 0x868>;
 403                         power-domains = <&zynqmp_firmware PD_ADMA>;
 404                 };
 405
 406                 lpd_dma_chan2: dma@ffa90000 {
 407                         status = "disabled";
 408                         compatible = "xlnx,zynqmp-dma-1.0";
 409                         reg = <0x0 0xffa90000 0x0 0x1000>;
 410                         interrupt-parent = <&gic>;
 411                         interrupts = <0 78 4>;
 412                         clock-names = "clk_main", "clk_apb";
 413                         xlnx,bus-width = <64>;
 414                         #stream-id-cells = <1>;
 415                         iommus = <&smmu 0x869>;
 416                         power-domains = <&zynqmp_firmware PD_ADMA>;
 417                 };
 418
 419                 lpd_dma_chan3: dma@ffaa0000 {
 420                         status = "disabled";
 421                         compatible = "xlnx,zynqmp-dma-1.0";
 422                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 423                         interrupt-parent = <&gic>;
 424                         interrupts = <0 79 4>;
 425                         clock-names = "clk_main", "clk_apb";
 426                         xlnx,bus-width = <64>;
 427                         #stream-id-cells = <1>;
 428                         iommus = <&smmu 0x86a>;
 429                         power-domains = <&zynqmp_firmware PD_ADMA>;
 430                 };
 431
 432                 lpd_dma_chan4: dma@ffab0000 {
 433                         status = "disabled";
 434                         compatible = "xlnx,zynqmp-dma-1.0";
 435                         reg = <0x0 0xffab0000 0x0 0x1000>;
 436                         interrupt-parent = <&gic>;
 437                         interrupts = <0 80 4>;
 438                         clock-names = "clk_main", "clk_apb";
 439                         xlnx,bus-width = <64>;
 440                         #stream-id-cells = <1>;
 441                         iommus = <&smmu 0x86b>;
 442                         power-domains = <&zynqmp_firmware PD_ADMA>;
 443                 };
 444
 445                 lpd_dma_chan5: dma@ffac0000 {
 446                         status = "disabled";
 447                         compatible = "xlnx,zynqmp-dma-1.0";
 448                         reg = <0x0 0xffac0000 0x0 0x1000>;
 449                         interrupt-parent = <&gic>;
 450                         interrupts = <0 81 4>;
 451                         clock-names = "clk_main", "clk_apb";
 452                         xlnx,bus-width = <64>;
 453                         #stream-id-cells = <1>;
 454                         iommus = <&smmu 0x86c>;
 455                         power-domains = <&zynqmp_firmware PD_ADMA>;
 456                 };
 457
 458                 lpd_dma_chan6: dma@ffad0000 {
 459                         status = "disabled";
 460                         compatible = "xlnx,zynqmp-dma-1.0";
 461                         reg = <0x0 0xffad0000 0x0 0x1000>;
 462                         interrupt-parent = <&gic>;
 463                         interrupts = <0 82 4>;
 464                         clock-names = "clk_main", "clk_apb";
 465                         xlnx,bus-width = <64>;
 466                         #stream-id-cells = <1>;
 467                         iommus = <&smmu 0x86d>;
 468                         power-domains = <&zynqmp_firmware PD_ADMA>;
 469                 };
 470
 471                 lpd_dma_chan7: dma@ffae0000 {
 472                         status = "disabled";
 473                         compatible = "xlnx,zynqmp-dma-1.0";
 474                         reg = <0x0 0xffae0000 0x0 0x1000>;
 475                         interrupt-parent = <&gic>;
 476                         interrupts = <0 83 4>;
 477                         clock-names = "clk_main", "clk_apb";
 478                         xlnx,bus-width = <64>;
 479                         #stream-id-cells = <1>;
 480                         iommus = <&smmu 0x86e>;
 481                         power-domains = <&zynqmp_firmware PD_ADMA>;
 482                 };
 483
 484                 lpd_dma_chan8: dma@ffaf0000 {
 485                         status = "disabled";
 486                         compatible = "xlnx,zynqmp-dma-1.0";
 487                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 488                         interrupt-parent = <&gic>;
 489                         interrupts = <0 84 4>;
 490                         clock-names = "clk_main", "clk_apb";
 491                         xlnx,bus-width = <64>;
 492                         #stream-id-cells = <1>;
 493                         iommus = <&smmu 0x86f>;
 494                         power-domains = <&zynqmp_firmware PD_ADMA>;
 495                 };
 496
 497                 mc: memory-controller@fd070000 {
 498                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 499                         reg = <0x0 0xfd070000 0x0 0x30000>;
 500                         interrupt-parent = <&gic>;
 501                         interrupts = <0 112 4>;
 502                 };
 503
 504                 nand0: nand@ff100000 {
 505                         compatible = "arasan,nfc-v3p10";
 506                         status = "disabled";
 507                         reg = <0x0 0xff100000 0x0 0x1000>;
 508                         clock-names = "clk_sys", "clk_flash";
 509                         interrupt-parent = <&gic>;
 510                         interrupts = <0 14 4>;
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         #stream-id-cells = <1>;
 514                         iommus = <&smmu 0x872>;
 515                         power-domains = <&zynqmp_firmware PD_NAND>;
 516                 };
 517
 518                 gem0: ethernet@ff0b0000 {
 519                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 520                         status = "disabled";
 521                         interrupt-parent = <&gic>;
 522                         interrupts = <0 57 4>, <0 57 4>;
 523                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 524                         clock-names = "pclk", "hclk", "tx_clk";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         #stream-id-cells = <1>;
 528                         iommus = <&smmu 0x874>;
 529                         power-domains = <&zynqmp_firmware PD_ETH_0>;
 530                 };
 531
 532                 gem1: ethernet@ff0c0000 {
 533                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 534                         status = "disabled";
 535                         interrupt-parent = <&gic>;
 536                         interrupts = <0 59 4>, <0 59 4>;
 537                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 538                         clock-names = "pclk", "hclk", "tx_clk";
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                         #stream-id-cells = <1>;
 542                         iommus = <&smmu 0x875>;
 543                         power-domains = <&zynqmp_firmware PD_ETH_1>;
 544                 };
 545
 546                 gem2: ethernet@ff0d0000 {
 547                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 548                         status = "disabled";
 549                         interrupt-parent = <&gic>;
 550                         interrupts = <0 61 4>, <0 61 4>;
 551                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 552                         clock-names = "pclk", "hclk", "tx_clk";
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         #stream-id-cells = <1>;
 556                         iommus = <&smmu 0x876>;
 557                         power-domains = <&zynqmp_firmware PD_ETH_2>;
 558                 };
 559
 560                 gem3: ethernet@ff0e0000 {
 561                         compatible = "cdns,zynqmp-gem", "cdns,gem";
 562                         status = "disabled";
 563                         interrupt-parent = <&gic>;
 564                         interrupts = <0 63 4>, <0 63 4>;
 565                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 566                         clock-names = "pclk", "hclk", "tx_clk";
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         #stream-id-cells = <1>;
 570                         iommus = <&smmu 0x877>;
 571                         power-domains = <&zynqmp_firmware PD_ETH_3>;
 572                 };
 573
 574                 gpio: gpio@ff0a0000 {
 575                         compatible = "xlnx,zynqmp-gpio-1.0";
 576                         status = "disabled";
 577                         #gpio-cells = <0x2>;
 578                         gpio-controller;
 579                         interrupt-parent = <&gic>;
 580                         interrupts = <0 16 4>;
 581                         interrupt-controller;
 582                         #interrupt-cells = <2>;
 583                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 584                         power-domains = <&zynqmp_firmware PD_GPIO>;
 585                 };
 586
 587                 i2c0: i2c@ff020000 {
 588                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 589                         status = "disabled";
 590                         interrupt-parent = <&gic>;
 591                         interrupts = <0 17 4>;
 592                         reg = <0x0 0xff020000 0x0 0x1000>;
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         power-domains = <&zynqmp_firmware PD_I2C_0>;
 596                 };
 597
 598                 i2c1: i2c@ff030000 {
 599                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 600                         status = "disabled";
 601                         interrupt-parent = <&gic>;
 602                         interrupts = <0 18 4>;
 603                         reg = <0x0 0xff030000 0x0 0x1000>;
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606                         power-domains = <&zynqmp_firmware PD_I2C_1>;
 607                 };
 608
 609                 ocm: memory-controller@ff960000 {
 610                         compatible = "xlnx,zynqmp-ocmc-1.0";
 611                         reg = <0x0 0xff960000 0x0 0x1000>;
 612                         interrupt-parent = <&gic>;
 613                         interrupts = <0 10 4>;
 614                 };
 615
 616                 pcie: pcie@fd0e0000 {
 617                         compatible = "xlnx,nwl-pcie-2.11";
 618                         status = "disabled";
 619                         #address-cells = <3>;
 620                         #size-cells = <2>;
 621                         #interrupt-cells = <1>;
 622                         msi-controller;
 623                         device_type = "pci";
 624                         interrupt-parent = <&gic>;
 625                         interrupts = <0 118 4>,
 626                                      <0 117 4>,
 627                                      <0 116 4>,
 628                                      <0 115 4>, /* MSI_1 [63...32] */
 629                                      <0 114 4>; /* MSI_0 [31...0] */
 630                         interrupt-names = "misc", "dummy", "intx",
 631                                           "msi1", "msi0";
 632                         msi-parent = <&pcie>;
 633                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 634                               <0x0 0xfd480000 0x0 0x1000>,
 635                               <0x80 0x00000000 0x0 0x1000000>;
 636                         reg-names = "breg", "pcireg", "cfg";
 637                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 638                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 639                         bus-range = <0x00 0xff>;
 640                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 641                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 642                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 643                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 644                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 645                         power-domains = <&zynqmp_firmware PD_PCIE>;
 646                         pcie_intc: legacy-interrupt-controller {
 647                                 interrupt-controller;
 648                                 #address-cells = <0>;
 649                                 #interrupt-cells = <1>;
 650                         };
 651                 };
 652
 653                 qspi: spi@ff0f0000 {
 654                         u-boot,dm-pre-reloc;
 655                         compatible = "xlnx,zynqmp-qspi-1.0";
 656                         status = "disabled";
 657                         clock-names = "ref_clk", "pclk";
 658                         interrupts = <0 15 4>;
 659                         interrupt-parent = <&gic>;
 660                         num-cs = <1>;
 661                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 662                               <0x0 0xc0000000 0x0 0x8000000>;
 663                         #address-cells = <1>;
 664                         #size-cells = <0>;
 665                         #stream-id-cells = <1>;
 666                         iommus = <&smmu 0x873>;
 667                         power-domains = <&zynqmp_firmware PD_QSPI>;
 668                 };
 669
 670                 rtc: rtc@ffa60000 {
 671                         compatible = "xlnx,zynqmp-rtc";
 672                         status = "disabled";
 673                         reg = <0x0 0xffa60000 0x0 0x100>;
 674                         interrupt-parent = <&gic>;
 675                         interrupts = <0 26 4>, <0 27 4>;
 676                         interrupt-names = "alarm", "sec";
 677                         calibration = <0x8000>;
 678                 };
 679
 680                 serdes: zynqmp_phy@fd400000 {
 681                         compatible = "xlnx,zynqmp-psgtr";
 682                         status = "disabled";
 683                         reg = <0x0 0xfd400000 0x0 0x40000>,
 684                               <0x0 0xfd3d0000 0x0 0x1000>,
 685                               <0x0 0xff5e0000 0x0 0x1000>;
 686                         reg-names = "serdes", "siou", "lpd";
 687                         nvmem-cells = <&soc_revision>;
 688                         nvmem-cell-names = "soc_revision";
 689                         resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
 690                                  <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
 691                                  <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
 692                                  <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
 693                                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
 694                                  <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
 695                                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
 696                                  <&zynqmp_reset ZYNQMP_RESET_DP>,
 697                                  <&zynqmp_reset ZYNQMP_RESET_GEM0>,
 698                                  <&zynqmp_reset ZYNQMP_RESET_GEM1>,
 699                                  <&zynqmp_reset ZYNQMP_RESET_GEM2>,
 700                                  <&zynqmp_reset ZYNQMP_RESET_GEM3>;
 701                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 702                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 703                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 704                                       "gem1_rst", "gem2_rst", "gem3_rst";
 705                         lane0: lane0 {
 706                                 #phy-cells = <4>;
 707                         };
 708                         lane1: lane1 {
 709                                 #phy-cells = <4>;
 710                         };
 711                         lane2: lane2 {
 712                                 #phy-cells = <4>;
 713                         };
 714                         lane3: lane3 {
 715                                 #phy-cells = <4>;
 716                         };
 717                 };
 718
 719                 sata: ahci@fd0c0000 {
 720                         compatible = "ceva,ahci-1v84";
 721                         status = "disabled";
 722                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 723                         interrupt-parent = <&gic>;
 724                         interrupts = <0 133 4>;
 725                         power-domains = <&zynqmp_firmware PD_SATA>;
 726                         #stream-id-cells = <4>;
 727                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 728                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 729                         /* dma-coherent; */
 730                 };
 731
 732                 sdhci0: mmc@ff160000 {
 733                         u-boot,dm-pre-reloc;
 734                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 735                         status = "disabled";
 736                         interrupt-parent = <&gic>;
 737                         interrupts = <0 48 4>;
 738                         reg = <0x0 0xff160000 0x0 0x1000>;
 739                         clock-names = "clk_xin", "clk_ahb";
 740                         xlnx,device_id = <0>;
 741                         #stream-id-cells = <1>;
 742                         iommus = <&smmu 0x870>;
 743                         power-domains = <&zynqmp_firmware PD_SD_0>;
 744                         nvmem-cells = <&soc_revision>;
 745                         nvmem-cell-names = "soc_revision";
 746                         #clock-cells = <1>;
 747                         clock-output-names = "clk_out_sd0", "clk_in_sd0";
 748                 };
 749
 750                 sdhci1: mmc@ff170000 {
 751                         u-boot,dm-pre-reloc;
 752                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 753                         status = "disabled";
 754                         interrupt-parent = <&gic>;
 755                         interrupts = <0 49 4>;
 756                         reg = <0x0 0xff170000 0x0 0x1000>;
 757                         clock-names = "clk_xin", "clk_ahb";
 758                         xlnx,device_id = <1>;
 759                         #stream-id-cells = <1>;
 760                         iommus = <&smmu 0x871>;
 761                         power-domains = <&zynqmp_firmware PD_SD_1>;
 762                         nvmem-cells = <&soc_revision>;
 763                         nvmem-cell-names = "soc_revision";
 764                         #clock-cells = <1>;
 765                         clock-output-names = "clk_out_sd1", "clk_in_sd1";
 766                 };
 767
 768                 pinctrl0: pinctrl@ff180000 {
 769                         compatible = "xlnx,pinctrl-zynqmp";
 770                         status = "disabled";
 771                         reg = <0x0 0xff180000 0x0 0x1000>;
 772                 };
 773
 774                 smmu: smmu@fd800000 {
 775                         compatible = "arm,mmu-500";
 776                         reg = <0x0 0xfd800000 0x0 0x20000>;
 777                         #iommu-cells = <1>;
 778                         status = "disabled";
 779                         #global-interrupts = <1>;
 780                         interrupt-parent = <&gic>;
 781                         interrupts = <0 155 4>,
 782                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 783                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 784                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 785                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 786                 };
 787
 788                 spi0: spi@ff040000 {
 789                         compatible = "cdns,spi-r1p6";
 790                         status = "disabled";
 791                         interrupt-parent = <&gic>;
 792                         interrupts = <0 19 4>;
 793                         reg = <0x0 0xff040000 0x0 0x1000>;
 794                         clock-names = "ref_clk", "pclk";
 795                         #address-cells = <1>;
 796                         #size-cells = <0>;
 797                         power-domains = <&zynqmp_firmware PD_SPI_0>;
 798                 };
 799
 800                 spi1: spi@ff050000 {
 801                         compatible = "cdns,spi-r1p6";
 802                         status = "disabled";
 803                         interrupt-parent = <&gic>;
 804                         interrupts = <0 20 4>;
 805                         reg = <0x0 0xff050000 0x0 0x1000>;
 806                         clock-names = "ref_clk", "pclk";
 807                         #address-cells = <1>;
 808                         #size-cells = <0>;
 809                         power-domains = <&zynqmp_firmware PD_SPI_1>;
 810                 };
 811
 812                 ttc0: timer@ff110000 {
 813                         compatible = "cdns,ttc";
 814                         status = "disabled";
 815                         interrupt-parent = <&gic>;
 816                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 817                         reg = <0x0 0xff110000 0x0 0x1000>;
 818                         timer-width = <32>;
 819                         power-domains = <&zynqmp_firmware PD_TTC_0>;
 820                 };
 821
 822                 ttc1: timer@ff120000 {
 823                         compatible = "cdns,ttc";
 824                         status = "disabled";
 825                         interrupt-parent = <&gic>;
 826                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 827                         reg = <0x0 0xff120000 0x0 0x1000>;
 828                         timer-width = <32>;
 829                         power-domains = <&zynqmp_firmware PD_TTC_1>;
 830                 };
 831
 832                 ttc2: timer@ff130000 {
 833                         compatible = "cdns,ttc";
 834                         status = "disabled";
 835                         interrupt-parent = <&gic>;
 836                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 837                         reg = <0x0 0xff130000 0x0 0x1000>;
 838                         timer-width = <32>;
 839                         power-domains = <&zynqmp_firmware PD_TTC_2>;
 840                 };
 841
 842                 ttc3: timer@ff140000 {
 843                         compatible = "cdns,ttc";
 844                         status = "disabled";
 845                         interrupt-parent = <&gic>;
 846                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 847                         reg = <0x0 0xff140000 0x0 0x1000>;
 848                         timer-width = <32>;
 849                         power-domains = <&zynqmp_firmware PD_TTC_3>;
 850                 };
 851
 852                 uart0: serial@ff000000 {
 853                         u-boot,dm-pre-reloc;
 854                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 855                         status = "disabled";
 856                         interrupt-parent = <&gic>;
 857                         interrupts = <0 21 4>;
 858                         reg = <0x0 0xff000000 0x0 0x1000>;
 859                         clock-names = "uart_clk", "pclk";
 860                         power-domains = <&zynqmp_firmware PD_UART_0>;
 861                 };
 862
 863                 uart1: serial@ff010000 {
 864                         u-boot,dm-pre-reloc;
 865                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 866                         status = "disabled";
 867                         interrupt-parent = <&gic>;
 868                         interrupts = <0 22 4>;
 869                         reg = <0x0 0xff010000 0x0 0x1000>;
 870                         clock-names = "uart_clk", "pclk";
 871                         power-domains = <&zynqmp_firmware PD_UART_1>;
 872                 };
 873
 874                 usb0: usb0@ff9d0000 {
 875                         #address-cells = <2>;
 876                         #size-cells = <2>;
 877                         status = "disabled";
 878                         compatible = "xlnx,zynqmp-dwc3";
 879                         reg = <0x0 0xff9d0000 0x0 0x100>;
 880                         clock-names = "bus_clk", "ref_clk";
 881                         power-domains = <&zynqmp_firmware PD_USB_0>;
 882                         ranges;
 883                         nvmem-cells = <&soc_revision>;
 884                         nvmem-cell-names = "soc_revision";
 885
 886                         dwc3_0: dwc3@fe200000 {
 887                                 compatible = "snps,dwc3";
 888                                 status = "disabled";
 889                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 890                                 interrupt-parent = <&gic>;
 891                                 interrupts = <0 65 4>, <0 69 4>;
 892                                 #stream-id-cells = <1>;
 893                                 iommus = <&smmu 0x860>;
 894                                 snps,quirk-frame-length-adjustment = <0x20>;
 895                                 snps,refclk_fladj;
 896                                 /* dma-coherent; */
 897                         };
 898                 };
 899
 900                 usb1: usb1@ff9e0000 {
 901                         #address-cells = <2>;
 902                         #size-cells = <2>;
 903                         status = "disabled";
 904                         compatible = "xlnx,zynqmp-dwc3";
 905                         reg = <0x0 0xff9e0000 0x0 0x100>;
 906                         clock-names = "bus_clk", "ref_clk";
 907                         power-domains = <&zynqmp_firmware PD_USB_1>;
 908                         ranges;
 909                         nvmem-cells = <&soc_revision>;
 910                         nvmem-cell-names = "soc_revision";
 911
 912                         dwc3_1: dwc3@fe300000 {
 913                                 compatible = "snps,dwc3";
 914                                 status = "disabled";
 915                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 916                                 interrupt-parent = <&gic>;
 917                                 interrupts = <0 70 4>, <0 74 4>;
 918                                 #stream-id-cells = <1>;
 919                                 iommus = <&smmu 0x861>;
 920                                 snps,quirk-frame-length-adjustment = <0x20>;
 921                                 snps,refclk_fladj;
 922                                 /* dma-coherent; */
 923                         };
 924                 };
 925
 926                 watchdog0: watchdog@fd4d0000 {
 927                         compatible = "cdns,wdt-r1p2";
 928                         status = "disabled";
 929                         interrupt-parent = <&gic>;
 930                         interrupts = <0 113 1>;
 931                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
 932                         timeout-sec = <60>;
 933                         reset-on-timeout;
 934                 };
 935
 936                 lpd_watchdog: watchdog@ff150000 {
 937                         compatible = "cdns,wdt-r1p2";
 938                         status = "disabled";
 939                         interrupt-parent = <&gic>;
 940                         interrupts = <0 52 1>;
 941                         reg = <0x0 0xff150000 0x0 0x1000>;
 942                         timeout-sec = <10>;
 943                 };
 944
 945                 xilinx_ams: ams@ffa50000 {
 946                         compatible = "xlnx,zynqmp-ams";
 947                         status = "disabled";
 948                         interrupt-parent = <&gic>;
 949                         interrupts = <0 56 4>;
 950                         interrupt-names = "ams-irq";
 951                         reg = <0x0 0xffa50000 0x0 0x800>;
 952                         reg-names = "ams-base";
 953                         #address-cells = <2>;
 954                         #size-cells = <2>;
 955                         #io-channel-cells = <1>;
 956                         ranges;
 957
 958                         ams_ps: ams_ps@ffa50800 {
 959                                 compatible = "xlnx,zynqmp-ams-ps";
 960                                 status = "disabled";
 961                                 reg = <0x0 0xffa50800 0x0 0x400>;
 962                         };
 963
 964                         ams_pl: ams_pl@ffa50c00 {
 965                                 compatible = "xlnx,zynqmp-ams-pl";
 966                                 status = "disabled";
 967                                 reg = <0x0 0xffa50c00 0x0 0x400>;
 968                         };
 969                 };
 970
 971                 xlnx_dpdma: dma@fd4c0000 {
 972                         compatible = "xlnx,dpdma";
 973                         status = "disabled";
 974                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
 975                         interrupts = <0 122 4>;
 976                         interrupt-parent = <&gic>;
 977                         clock-names = "axi_clk";
 978                         power-domains = <&zynqmp_firmware PD_DP>;
 979                         dma-channels = <6>;
 980                         #dma-cells = <1>;
 981                         dma-video0channel {
 982                                 compatible = "xlnx,video0";
 983                         };
 984                         dma-video1channel {
 985                                 compatible = "xlnx,video1";
 986                         };
 987                         dma-video2channel {
 988                                 compatible = "xlnx,video2";
 989                         };
 990                         dma-graphicschannel {
 991                                 compatible = "xlnx,graphics";
 992                         };
 993                         dma-audio0channel {
 994                                 compatible = "xlnx,audio0";
 995                         };
 996                         dma-audio1channel {
 997                                 compatible = "xlnx,audio1";
 998                         };
 999                 };
1000
1001                 zynqmp_dpsub: zynqmp-display@fd4a0000 {
1002                         compatible = "xlnx,zynqmp-dpsub-1.7";
1003                         status = "disabled";
1004                         reg = <0x0 0xfd4a0000 0x0 0x1000>,
1005                               <0x0 0xfd4aa000 0x0 0x1000>,
1006                               <0x0 0xfd4ab000 0x0 0x1000>,
1007                               <0x0 0xfd4ac000 0x0 0x1000>;
1008                         reg-names = "dp", "blend", "av_buf", "aud";
1009                         interrupts = <0 119 4>;
1010                         interrupt-parent = <&gic>;
1011
1012                         clock-names = "dp_apb_clk", "dp_aud_clk",
1013                                       "dp_vtc_pixel_clk_in";
1014
1015                         power-domains = <&zynqmp_firmware PD_DP>;
1016
1017                         vid-layer {
1018                                 dma-names = "vid0", "vid1", "vid2";
1019                                 dmas = <&xlnx_dpdma 0>,
1020                                        <&xlnx_dpdma 1>,
1021                                        <&xlnx_dpdma 2>;
1022                         };
1023
1024                         gfx-layer {
1025                                 dma-names = "gfx0";
1026                                 dmas = <&xlnx_dpdma 3>;
1027                         };
1028
1029                         /* dummy node to indicate there's no child i2c device */
1030                         i2c-bus {
1031                         };
1032
1033                         zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
1034                                 compatible = "xlnx,dp-snd-codec";
1035                                 clock-names = "aud_clk";
1036                         };
1037
1038                         zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
1039                                 compatible = "xlnx,dp-snd-pcm";
1040                                 dmas = <&xlnx_dpdma 4>;
1041                                 dma-names = "tx";
1042                         };
1043
1044                         zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
1045                                 compatible = "xlnx,dp-snd-pcm";
1046                                 dmas = <&xlnx_dpdma 5>;
1047                                 dma-names = "tx";
1048                         };
1049
1050                         zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
1051                                 compatible = "xlnx,dp-snd-card";
1052                                 xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
1053                                                   <&zynqmp_dp_snd_pcm1>;
1054                                 xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
1055                         };
1056                 };
1057         };
1058 };