arch/arm/dts/zynqmp-zcu106-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU106
   4  *
   5  * (C) Copyright 2016 - 2020, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 / {
  19         model = "ZynqMP ZCU106 RevA";
  20         compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39                 xlnx,eeprom = &eeprom;
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 autorepeat;
  50                 sw19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_DOWN>;
  54                         wakeup-source;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat-led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         ina226-u76 {
  69                 compatible = "iio-hwmon";
  70                 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
  71         };
  72         ina226-u77 {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
  75         };
  76         ina226-u78 {
  77                 compatible = "iio-hwmon";
  78                 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
  79         };
  80         ina226-u87 {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
  83         };
  84         ina226-u85 {
  85                 compatible = "iio-hwmon";
  86                 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
  87         };
  88         ina226-u86 {
  89                 compatible = "iio-hwmon";
  90                 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
  91         };
  92         ina226-u93 {
  93                 compatible = "iio-hwmon";
  94                 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
  95         };
  96         ina226-u88 {
  97                 compatible = "iio-hwmon";
  98                 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
  99         };
 100         ina226-u15 {
 101                 compatible = "iio-hwmon";
 102                 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
 103         };
 104         ina226-u92 {
 105                 compatible = "iio-hwmon";
 106                 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
 107         };
 108         ina226-u79 {
 109                 compatible = "iio-hwmon";
 110                 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 111         };
 112         ina226-u81 {
 113                 compatible = "iio-hwmon";
 114                 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
 115         };
 116         ina226-u80 {
 117                 compatible = "iio-hwmon";
 118                 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
 119         };
 120         ina226-u84 {
 121                 compatible = "iio-hwmon";
 122                 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 123         };
 124         ina226-u16 {
 125                 compatible = "iio-hwmon";
 126                 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
 127         };
 128         ina226-u65 {
 129                 compatible = "iio-hwmon";
 130                 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 131         };
 132         ina226-u74 {
 133                 compatible = "iio-hwmon";
 134                 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 135         };
 136         ina226-u75 {
 137                 compatible = "iio-hwmon";
 138                 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 139         };
 140 };
 141
 142 &can1 {
 143         status = "okay";
 144 };
 145
 146 &dcc {
 147         status = "okay";
 148 };
 149
 150 &fpd_dma_chan1 {
 151         status = "okay";
 152 };
 153
 154 &fpd_dma_chan2 {
 155         status = "okay";
 156 };
 157
 158 &fpd_dma_chan3 {
 159         status = "okay";
 160 };
 161
 162 &fpd_dma_chan4 {
 163         status = "okay";
 164 };
 165
 166 &fpd_dma_chan5 {
 167         status = "okay";
 168 };
 169
 170 &fpd_dma_chan6 {
 171         status = "okay";
 172 };
 173
 174 &fpd_dma_chan7 {
 175         status = "okay";
 176 };
 177
 178 &fpd_dma_chan8 {
 179         status = "okay";
 180 };
 181
 182 &gem3 {
 183         status = "okay";
 184         phy-handle = <&phy0>;
 185         phy-mode = "rgmii-id";
 186         phy0: ethernet-phy@c {
 187                 reg = <0xc>;
 188                 ti,rx-internal-delay = <0x8>;
 189                 ti,tx-internal-delay = <0xa>;
 190                 ti,fifo-depth = <0x1>;
 191                 ti,dp83867-rxctrl-strap-quirk;
 192         };
 193 };
 194
 195 &gpio {
 196         status = "okay";
 197 };
 198
 199 &gpu {
 200         status = "okay";
 201 };
 202
 203 &i2c0 {
 204         status = "okay";
 205         clock-frequency = <400000>;
 206
 207         tca6416_u97: gpio@20 {
 208                 compatible = "ti,tca6416";
 209                 reg = <0x20>;
 210                 gpio-controller; /* interrupt not connected */
 211                 #gpio-cells = <2>;
 212                 /*
 213                  * IRQ not connected
 214                  * Lines:
 215                  * 0 - SFP_SI5328_INT_ALM
 216                  * 1 - HDMI_SI5328_INT_ALM
 217                  * 5 - IIC_MUX_RESET_B
 218                  * 6 - GEM3_EXP_RESET_B
 219                  * 10 - FMC_HPC0_PRSNT_M2C_B
 220                  * 11 - FMC_HPC1_PRSNT_M2C_B
 221                  * 2-4, 7, 12-17 - not connected
 222                  */
 223         };
 224
 225         tca6416_u61: gpio@21 {
 226                 compatible = "ti,tca6416";
 227                 reg = <0x21>;
 228                 gpio-controller;
 229                 #gpio-cells = <2>;
 230                 /*
 231                  * IRQ not connected
 232                  * Lines:
 233                  * 0 - VCCPSPLL_EN
 234                  * 1 - MGTRAVCC_EN
 235                  * 2 - MGTRAVTT_EN
 236                  * 3 - VCCPSDDRPLL_EN
 237                  * 4 - MIO26_PMU_INPUT_LS
 238                  * 5 - PL_PMBUS_ALERT
 239                  * 6 - PS_PMBUS_ALERT
 240                  * 7 - MAXIM_PMBUS_ALERT
 241                  * 10 - PL_DDR4_VTERM_EN
 242                  * 11 - PL_DDR4_VPP_2V5_EN
 243                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 244                  * 13 - PS_DIMM_SUSPEND_EN
 245                  * 14 - PS_DDR4_VTERM_EN
 246                  * 15 - PS_DDR4_VPP_2V5_EN
 247                  * 16 - 17 - not connected
 248                  */
 249         };
 250
 251         i2c-mux@75 { /* u60 */
 252                 compatible = "nxp,pca9544";
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 reg = <0x75>;
 256                 i2c@0 {
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         reg = <0>;
 260                         /* PS_PMBUS */
 261                         u76: ina226@40 { /* u76 */
 262                                 compatible = "ti,ina226";
 263                                 #io-channel-cells = <1>;
 264                                 label = "ina226-u76";
 265                                 reg = <0x40>;
 266                                 shunt-resistor = <5000>;
 267                         };
 268                         u77: ina226@41 { /* u77 */
 269                                 compatible = "ti,ina226";
 270                                 #io-channel-cells = <1>;
 271                                 label = "ina226-u77";
 272                                 reg = <0x41>;
 273                                 shunt-resistor = <5000>;
 274                         };
 275                         u78: ina226@42 { /* u78 */
 276                                 compatible = "ti,ina226";
 277                                 #io-channel-cells = <1>;
 278                                 label = "ina226-u78";
 279                                 reg = <0x42>;
 280                                 shunt-resistor = <5000>;
 281                         };
 282                         u87: ina226@43 { /* u87 */
 283                                 compatible = "ti,ina226";
 284                                 #io-channel-cells = <1>;
 285                                 label = "ina226-u87";
 286                                 reg = <0x43>;
 287                                 shunt-resistor = <5000>;
 288                         };
 289                         u85: ina226@44 { /* u85 */
 290                                 compatible = "ti,ina226";
 291                                 #io-channel-cells = <1>;
 292                                 label = "ina226-u85";
 293                                 reg = <0x44>;
 294                                 shunt-resistor = <5000>;
 295                         };
 296                         u86: ina226@45 { /* u86 */
 297                                 compatible = "ti,ina226";
 298                                 #io-channel-cells = <1>;
 299                                 label = "ina226-u86";
 300                                 reg = <0x45>;
 301                                 shunt-resistor = <5000>;
 302                         };
 303                         u93: ina226@46 { /* u93 */
 304                                 compatible = "ti,ina226";
 305                                 #io-channel-cells = <1>;
 306                                 label = "ina226-u93";
 307                                 reg = <0x46>;
 308                                 shunt-resistor = <5000>;
 309                         };
 310                         u88: ina226@47 { /* u88 */
 311                                 compatible = "ti,ina226";
 312                                 #io-channel-cells = <1>;
 313                                 label = "ina226-u88";
 314                                 reg = <0x47>;
 315                                 shunt-resistor = <5000>;
 316                         };
 317                         u15: ina226@4a { /* u15 */
 318                                 compatible = "ti,ina226";
 319                                 #io-channel-cells = <1>;
 320                                 label = "ina226-u15";
 321                                 reg = <0x4a>;
 322                                 shunt-resistor = <5000>;
 323                         };
 324                         u92: ina226@4b { /* u92 */
 325                                 compatible = "ti,ina226";
 326                                 #io-channel-cells = <1>;
 327                                 label = "ina226-u92";
 328                                 reg = <0x4b>;
 329                                 shunt-resistor = <5000>;
 330                         };
 331                 };
 332                 i2c@1 {
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         reg = <1>;
 336                         /* PL_PMBUS */
 337                         u79: ina226@40 { /* u79 */
 338                                 compatible = "ti,ina226";
 339                                 #io-channel-cells = <1>;
 340                                 label = "ina226-u79";
 341                                 reg = <0x40>;
 342                                 shunt-resistor = <2000>;
 343                         };
 344                         u81: ina226@41 { /* u81 */
 345                                 compatible = "ti,ina226";
 346                                 #io-channel-cells = <1>;
 347                                 label = "ina226-u81";
 348                                 reg = <0x41>;
 349                                 shunt-resistor = <5000>;
 350                         };
 351                         u80: ina226@42 { /* u80 */
 352                                 compatible = "ti,ina226";
 353                                 #io-channel-cells = <1>;
 354                                 label = "ina226-u80";
 355                                 reg = <0x42>;
 356                                 shunt-resistor = <5000>;
 357                         };
 358                         u84: ina226@43 { /* u84 */
 359                                 compatible = "ti,ina226";
 360                                 #io-channel-cells = <1>;
 361                                 label = "ina226-u84";
 362                                 reg = <0x43>;
 363                                 shunt-resistor = <5000>;
 364                         };
 365                         u16: ina226@44 { /* u16 */
 366                                 compatible = "ti,ina226";
 367                                 #io-channel-cells = <1>;
 368                                 label = "ina226-u16";
 369                                 reg = <0x44>;
 370                                 shunt-resistor = <5000>;
 371                         };
 372                         u65: ina226@45 { /* u65 */
 373                                 compatible = "ti,ina226";
 374                                 #io-channel-cells = <1>;
 375                                 label = "ina226-u65";
 376                                 reg = <0x45>;
 377                                 shunt-resistor = <5000>;
 378                         };
 379                         u74: ina226@46 { /* u74 */
 380                                 compatible = "ti,ina226";
 381                                 #io-channel-cells = <1>;
 382                                 label = "ina226-u74";
 383                                 reg = <0x46>;
 384                                 shunt-resistor = <5000>;
 385                         };
 386                         u75: ina226@47 { /* u75 */
 387                                 compatible = "ti,ina226";
 388                                 #io-channel-cells = <1>;
 389                                 label = "ina226-u75";
 390                                 reg = <0x47>;
 391                                 shunt-resistor = <5000>;
 392                         };
 393                 };
 394                 i2c@2 {
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         reg = <2>;
 398                         /* MAXIM_PMBUS - 00 */
 399                         max15301@a { /* u46 */
 400                                 compatible = "maxim,max15301";
 401                                 reg = <0xa>;
 402                         };
 403                         max15303@b { /* u4 */
 404                                 compatible = "maxim,max15303";
 405                                 reg = <0xb>;
 406                         };
 407                         max15303@10 { /* u13 */
 408                                 compatible = "maxim,max15303";
 409                                 reg = <0x10>;
 410                         };
 411                         max15301@13 { /* u47 */
 412                                 compatible = "maxim,max15301";
 413                                 reg = <0x13>;
 414                         };
 415                         max15303@14 { /* u7 */
 416                                 compatible = "maxim,max15303";
 417                                 reg = <0x14>;
 418                         };
 419                         max15303@15 { /* u6 */
 420                                 compatible = "maxim,max15303";
 421                                 reg = <0x15>;
 422                         };
 423                         max15303@16 { /* u10 */
 424                                 compatible = "maxim,max15303";
 425                                 reg = <0x16>;
 426                         };
 427                         max15303@17 { /* u9 */
 428                                 compatible = "maxim,max15303";
 429                                 reg = <0x17>;
 430                         };
 431                         max15301@18 { /* u63 */
 432                                 compatible = "maxim,max15301";
 433                                 reg = <0x18>;
 434                         };
 435                         max15303@1a { /* u49 */
 436                                 compatible = "maxim,max15303";
 437                                 reg = <0x1a>;
 438                         };
 439                         max15303@1b { /* u8 */
 440                                 compatible = "maxim,max15303";
 441                                 reg = <0x1b>;
 442                         };
 443                         max15303@1d { /* u18 */
 444                                 compatible = "maxim,max15303";
 445                                 reg = <0x1d>;
 446                         };
 447
 448                         max20751@72 { /* u95 */
 449                                 compatible = "maxim,max20751";
 450                                 reg = <0x72>;
 451                         };
 452                         max20751@73 { /* u96 */
 453                                 compatible = "maxim,max20751";
 454                                 reg = <0x73>;
 455                         };
 456                 };
 457                 /* Bus 3 is not connected */
 458         };
 459 };
 460
 461 &i2c1 {
 462         status = "okay";
 463         clock-frequency = <400000>;
 464
 465         /* PL i2c via PCA9306 - u45 */
 466         i2c-mux@74 { /* u34 */
 467                 compatible = "nxp,pca9548";
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 reg = <0x74>;
 471                 i2c@0 {
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         reg = <0>;
 475                         /*
 476                          * IIC_EEPROM 1kB memory which uses 256B blocks
 477                          * where every block has different address.
 478                          *    0 - 256B address 0x54
 479                          * 256B - 512B address 0x55
 480                          * 512B - 768B address 0x56
 481                          * 768B - 1024B address 0x57
 482                          */
 483                         eeprom: eeprom@54 { /* u23 */
 484                                 compatible = "atmel,24c08";
 485                                 reg = <0x54>;
 486                         };
 487                 };
 488                 i2c@1 {
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         reg = <1>;
 492                         si5341: clock-generator@36 { /* SI5341 - u69 */
 493                                 compatible = "si5341";
 494                                 reg = <0x36>;
 495                         };
 496
 497                 };
 498                 i2c@2 {
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501                         reg = <2>;
 502                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 503                                 #clock-cells = <0>;
 504                                 compatible = "silabs,si570";
 505                                 reg = <0x5d>;
 506                                 temperature-stability = <50>;
 507                                 factory-fout = <300000000>;
 508                                 clock-frequency = <300000000>;
 509                                 clock-output-names = "si570_user";
 510                         };
 511                 };
 512                 i2c@3 {
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         reg = <3>;
 516                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 517                                 #clock-cells = <0>;
 518                                 compatible = "silabs,si570";
 519                                 reg = <0x5d>;
 520                                 temperature-stability = <50>; /* copy from zc702 */
 521                                 factory-fout = <156250000>;
 522                                 clock-frequency = <148500000>;
 523                                 clock-output-names = "si570_mgt";
 524                         };
 525                 };
 526                 i2c@4 {
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         reg = <4>;
 530                         si5328: clock-generator@69 {/* SI5328 - u20 */
 531                                 compatible = "silabs,si5328";
 532                                 reg = <0x69>;
 533                         };
 534                 };
 535                 i2c@5 {
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         reg = <5>; /* FAN controller */
 539                         temp@4c {/* lm96163 - u128 */
 540                                 compatible = "national,lm96163";
 541                                 reg = <0x4c>;
 542                         };
 543                 };
 544                 /* 6 - 7 unconnected */
 545         };
 546
 547         i2c-mux@75 {
 548                 compatible = "nxp,pca9548"; /* u135 */
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 reg = <0x75>;
 552
 553                 i2c@0 {
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         reg = <0>;
 557                         /* HPC0_IIC */
 558                 };
 559                 i2c@1 {
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         reg = <1>;
 563                         /* HPC1_IIC */
 564                 };
 565                 i2c@2 {
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         reg = <2>;
 569                         /* SYSMON */
 570                 };
 571                 i2c@3 {
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         reg = <3>;
 575                         /* DDR4 SODIMM */
 576                 };
 577                 i2c@4 {
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         reg = <4>;
 581                         /* SEP 3 */
 582                 };
 583                 i2c@5 {
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         reg = <5>;
 587                         /* SEP 2 */
 588                 };
 589                 i2c@6 {
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                         reg = <6>;
 593                         /* SEP 1 */
 594                 };
 595                 i2c@7 {
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         reg = <7>;
 599                         /* SEP 0 */
 600                 };
 601         };
 602 };
 603
 604 &qspi {
 605         status = "okay";
 606         is-dual = <1>;
 607         flash@0 {
 608                 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 609                 #address-cells = <1>;
 610                 #size-cells = <1>;
 611                 reg = <0x0>;
 612                 spi-tx-bus-width = <1>;
 613                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 614                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 615                 partition@0 { /* for testing purpose */
 616                         label = "qspi-fsbl-uboot";
 617                         reg = <0x0 0x100000>;
 618                 };
 619                 partition@100000 { /* for testing purpose */
 620                         label = "qspi-linux";
 621                         reg = <0x100000 0x500000>;
 622                 };
 623                 partition@600000 { /* for testing purpose */
 624                         label = "qspi-device-tree";
 625                         reg = <0x600000 0x20000>;
 626                 };
 627                 partition@620000 { /* for testing purpose */
 628                         label = "qspi-rootfs";
 629                         reg = <0x620000 0x5E0000>;
 630                 };
 631         };
 632 };
 633
 634 &rtc {
 635         status = "okay";
 636 };
 637
 638 &sata {
 639         status = "okay";
 640         /* SATA OOB timing settings */
 641         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 642         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 643         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 644         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 645         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 646         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 647         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 648         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 649         phy-names = "sata-phy";
 650         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 651 };
 652
 653 /* SD1 with level shifter */
 654 &sdhci1 {
 655         status = "okay";
 656         /*
 657          * This property should be removed for supporting UHS mode
 658          */
 659         no-1-8-v;
 660         xlnx,mio_bank = <1>;
 661 };
 662
 663 &serdes {
 664         status = "okay";
 665 };
 666
 667 &uart0 {
 668         status = "okay";
 669 };
 670
 671 &uart1 {
 672         status = "okay";
 673 };
 674
 675 /* ULPI SMSC USB3320 */
 676 &usb0 {
 677         status = "okay";
 678 };
 679
 680 &dwc3_0 {
 681         status = "okay";
 682         dr_mode = "host";
 683         snps,usb3_lpm_capable;
 684         phy-names = "usb3-phy";
 685         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 686 };
 687
 688 &watchdog0 {
 689         status = "okay";
 690 };