arch/arm/dts/zynqmp-mini-emmc0.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP Mini Configuration
   4  *
   5  * (C) Copyright 2018, Xilinx, Inc.
   6  *
   7  * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         model = "ZynqMP MINI EMMC0";
  14         compatible = "xlnx,zynqmp";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &dcc;
  20                 mmc0 = &sdhci0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25         };
  26
  27         memory@0 {
  28                 device_type = "memory";
  29                 reg = <0x0 0x0 0x0 0x20000000>;
  30         };
  31
  32         dcc: dcc {
  33                 compatible = "arm,dcc";
  34                 status = "disabled";
  35                 u-boot,dm-pre-reloc;
  36         };
  37
  38         clk_xin: clk_xin {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 clock-frequency = <200000000>;
  42         };
  43
  44         amba: amba {
  45                 compatible = "simple-bus";
  46                 #address-cells = <2>;
  47                 #size-cells = <2>;
  48                 ranges;
  49
  50                 sdhci0: sdhci@ff160000 {
  51                         u-boot,dm-pre-reloc;
  52                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
  53                         status = "disabled";
  54                         reg = <0x0 0xff160000 0x0 0x1000>;
  55                         clock-names = "clk_xin", "clk_ahb";
  56                         clocks = <&clk_xin &clk_xin>;
  57                         xlnx,device_id = <0>;
  58                 };
  59         };
  60 };
  61
  62 &dcc {
  63         status = "okay";
  64 };
  65
  66 &sdhci0 {
  67         status = "okay";
  68 };