arch/arm/dts/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   9 #include <dt-bindings/clock/sun8i-de2.h>
  10 #include <dt-bindings/clock/sun8i-tcon-top.h>
  11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  13 #include <dt-bindings/reset/sun8i-de2.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "arm,cortex-a53";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         enable-method = "psci";
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         compatible = "arm,cortex-a53";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <2>;
  42                         enable-method = "psci";
  43                 };
  44
  45                 cpu3: cpu@3 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         reg = <3>;
  49                         enable-method = "psci";
  50                 };
  51         };
  52
  53         de: display-engine {
  54                 compatible = "allwinner,sun50i-h6-display-engine";
  55                 allwinner,pipelines = <&mixer0>;
  56                 status = "disabled";
  57         };
  58
  59         iosc: internal-osc-clk {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <16000000>;
  63                 clock-accuracy = <300000000>;
  64                 clock-output-names = "iosc";
  65         };
  66
  67         osc24M: osc24M_clk {
  68                 #clock-cells = <0>;
  69                 compatible = "fixed-clock";
  70                 clock-frequency = <24000000>;
  71                 clock-output-names = "osc24M";
  72         };
  73
  74         osc32k: osc32k_clk {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-clock";
  77                 clock-frequency = <32768>;
  78                 clock-output-names = "osc32k";
  79         };
  80
  81         psci {
  82                 compatible = "arm,psci-0.2";
  83                 method = "smc";
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv8-timer";
  88                 interrupts = <GIC_PPI 13
  89                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  90                              <GIC_PPI 14
  91                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  92                              <GIC_PPI 11
  93                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  94                              <GIC_PPI 10
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  96         };
  97
  98         soc {
  99                 compatible = "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 bus@1000000 {
 105                         compatible = "allwinner,sun50i-h6-de3",
 106                                      "allwinner,sun50i-a64-de2";
 107                         reg = <0x1000000 0x400000>;
 108                         allwinner,sram = <&de2_sram 1>;
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         ranges = <0 0x1000000 0x400000>;
 112
 113                         display_clocks: clock@0 {
 114                                 compatible = "allwinner,sun50i-h6-de3-clk";
 115                                 reg = <0x0 0x10000>;
 116                                 clocks = <&ccu CLK_DE>,
 117                                          <&ccu CLK_BUS_DE>;
 118                                 clock-names = "mod",
 119                                               "bus";
 120                                 resets = <&ccu RST_BUS_DE>;
 121                                 #clock-cells = <1>;
 122                                 #reset-cells = <1>;
 123                         };
 124
 125                         mixer0: mixer@100000 {
 126                                 compatible = "allwinner,sun50i-h6-de3-mixer-0";
 127                                 reg = <0x100000 0x100000>;
 128                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 129                                          <&display_clocks CLK_MIXER0>;
 130                                 clock-names = "bus",
 131                                               "mod";
 132                                 resets = <&display_clocks RST_MIXER0>;
 133
 134                                 ports {
 135                                         #address-cells = <1>;
 136                                         #size-cells = <0>;
 137
 138                                         mixer0_out: port@1 {
 139                                                 reg = <1>;
 140
 141                                                 mixer0_out_tcon_top_mixer0: endpoint {
 142                                                         remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 143                                                 };
 144                                         };
 145                                 };
 146                         };
 147                 };
 148
 149                 video-codec@1c0e000 {
 150                         compatible = "allwinner,sun50i-h6-video-engine";
 151                         reg = <0x01c0e000 0x2000>;
 152                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 153                                  <&ccu CLK_MBUS_VE>;
 154                         clock-names = "ahb", "mod", "ram";
 155                         resets = <&ccu RST_BUS_VE>;
 156                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 157                         allwinner,sram = <&ve_sram 1>;
 158                 };
 159
 160                 syscon: syscon@3000000 {
 161                         compatible = "allwinner,sun50i-h6-system-control",
 162                                      "allwinner,sun50i-a64-system-control";
 163                         reg = <0x03000000 0x1000>;
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         ranges;
 167
 168                         sram_c: sram@28000 {
 169                                 compatible = "mmio-sram";
 170                                 reg = <0x00028000 0x1e000>;
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 ranges = <0 0x00028000 0x1e000>;
 174
 175                                 de2_sram: sram-section@0 {
 176                                         compatible = "allwinner,sun50i-h6-sram-c",
 177                                                      "allwinner,sun50i-a64-sram-c";
 178                                         reg = <0x0000 0x1e000>;
 179                                 };
 180                         };
 181
 182                         sram_c1: sram@1a00000 {
 183                                 compatible = "mmio-sram";
 184                                 reg = <0x01a00000 0x200000>;
 185                                 #address-cells = <1>;
 186                                 #size-cells = <1>;
 187                                 ranges = <0 0x01a00000 0x200000>;
 188
 189                                 ve_sram: sram-section@0 {
 190                                         compatible = "allwinner,sun50i-h6-sram-c1",
 191                                                      "allwinner,sun4i-a10-sram-c1";
 192                                         reg = <0x000000 0x200000>;
 193                                 };
 194                         };
 195                 };
 196
 197                 ccu: clock@3001000 {
 198                         compatible = "allwinner,sun50i-h6-ccu";
 199                         reg = <0x03001000 0x1000>;
 200                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
 201                         clock-names = "hosc", "losc", "iosc";
 202                         #clock-cells = <1>;
 203                         #reset-cells = <1>;
 204                 };
 205
 206                 dma: dma-controller@3002000 {
 207                         compatible = "allwinner,sun50i-h6-dma";
 208                         reg = <0x03002000 0x1000>;
 209                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 210                         clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
 211                         clock-names = "bus", "mbus";
 212                         dma-channels = <16>;
 213                         dma-requests = <46>;
 214                         resets = <&ccu RST_BUS_DMA>;
 215                         #dma-cells = <1>;
 216                 };
 217
 218                 sid: sid@3006000 {
 219                         compatible = "allwinner,sun50i-h6-sid";
 220                         reg = <0x03006000 0x400>;
 221                 };
 222
 223                 watchdog: watchdog@30090a0 {
 224                         compatible = "allwinner,sun50i-h6-wdt",
 225                                      "allwinner,sun6i-a31-wdt";
 226                         reg = <0x030090a0 0x20>;
 227                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 228                         /* Broken on some H6 boards */
 229                         status = "disabled";
 230                 };
 231
 232                 pio: pinctrl@300b000 {
 233                         compatible = "allwinner,sun50i-h6-pinctrl";
 234                         reg = <0x0300b000 0x400>;
 235                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 239                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
 240                         clock-names = "apb", "hosc", "losc";
 241                         gpio-controller;
 242                         #gpio-cells = <3>;
 243                         interrupt-controller;
 244                         #interrupt-cells = <3>;
 245
 246                         ext_rgmii_pins: rgmii-pins {
 247                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 248                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 249                                        "PD11", "PD12", "PD13", "PD19", "PD20";
 250                                 function = "emac";
 251                                 drive-strength = <40>;
 252                         };
 253
 254                         hdmi_pins: hdmi-pins {
 255                                 pins = "PH8", "PH9", "PH10";
 256                                 function = "hdmi";
 257                         };
 258
 259                         mmc0_pins: mmc0-pins {
 260                                 pins = "PF0", "PF1", "PF2", "PF3",
 261                                        "PF4", "PF5";
 262                                 function = "mmc0";
 263                                 drive-strength = <30>;
 264                                 bias-pull-up;
 265                         };
 266
 267                         /*
 268                          * /omit-if-no-ref/ isn't supported by U-boot
 269                          * keep this comment to avoid bad sync with Linux
 270                          */
 271                         mmc1_pins: mmc1-pins {
 272                                 pins = "PG0", "PG1", "PG2", "PG3",
 273                                        "PG4", "PG5";
 274                                 function = "mmc1";
 275                                 drive-strength = <30>;
 276                                 bias-pull-up;
 277                         };
 278
 279                         mmc2_pins: mmc2-pins {
 280                                 pins = "PC1", "PC4", "PC5", "PC6",
 281                                        "PC7", "PC8", "PC9", "PC10",
 282                                        "PC11", "PC12", "PC13", "PC14";
 283                                 function = "mmc2";
 284                                 drive-strength = <30>;
 285                                 bias-pull-up;
 286                         };
 287
 288                         uart0_ph_pins: uart0-ph-pins {
 289                                 pins = "PH0", "PH1";
 290                                 function = "uart0";
 291                         };
 292                 };
 293
 294                 gic: interrupt-controller@3021000 {
 295                         compatible = "arm,gic-400";
 296                         reg = <0x03021000 0x1000>,
 297                               <0x03022000 0x2000>,
 298                               <0x03024000 0x2000>,
 299                               <0x03026000 0x2000>;
 300                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 301                         interrupt-controller;
 302                         #interrupt-cells = <3>;
 303                 };
 304
 305                 mmc0: mmc@4020000 {
 306                         compatible = "allwinner,sun50i-h6-mmc",
 307                                      "allwinner,sun50i-a64-mmc";
 308                         reg = <0x04020000 0x1000>;
 309                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 310                         clock-names = "ahb", "mmc";
 311                         resets = <&ccu RST_BUS_MMC0>;
 312                         reset-names = "ahb";
 313                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 314                         pinctrl-names = "default";
 315                         pinctrl-0 = <&mmc0_pins>;
 316                         status = "disabled";
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                 };
 320
 321                 mmc1: mmc@4021000 {
 322                         compatible = "allwinner,sun50i-h6-mmc",
 323                                      "allwinner,sun50i-a64-mmc";
 324                         reg = <0x04021000 0x1000>;
 325                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 326                         clock-names = "ahb", "mmc";
 327                         resets = <&ccu RST_BUS_MMC1>;
 328                         reset-names = "ahb";
 329                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 330                         pinctrl-names = "default";
 331                         pinctrl-0 = <&mmc1_pins>;
 332                         status = "disabled";
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                 };
 336
 337                 mmc2: mmc@4022000 {
 338                         compatible = "allwinner,sun50i-h6-emmc",
 339                                      "allwinner,sun50i-a64-emmc";
 340                         reg = <0x04022000 0x1000>;
 341                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 342                         clock-names = "ahb", "mmc";
 343                         resets = <&ccu RST_BUS_MMC2>;
 344                         reset-names = "ahb";
 345                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 346                         pinctrl-names = "default";
 347                         pinctrl-0 = <&mmc2_pins>;
 348                         status = "disabled";
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                 };
 352
 353                 uart0: serial@5000000 {
 354                         compatible = "snps,dw-apb-uart";
 355                         reg = <0x05000000 0x400>;
 356                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 357                         reg-shift = <2>;
 358                         reg-io-width = <4>;
 359                         clocks = <&ccu CLK_BUS_UART0>;
 360                         resets = <&ccu RST_BUS_UART0>;
 361                         status = "disabled";
 362                 };
 363
 364                 uart1: serial@5000400 {
 365                         compatible = "snps,dw-apb-uart";
 366                         reg = <0x05000400 0x400>;
 367                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 368                         reg-shift = <2>;
 369                         reg-io-width = <4>;
 370                         clocks = <&ccu CLK_BUS_UART1>;
 371                         resets = <&ccu RST_BUS_UART1>;
 372                         status = "disabled";
 373                 };
 374
 375                 uart2: serial@5000800 {
 376                         compatible = "snps,dw-apb-uart";
 377                         reg = <0x05000800 0x400>;
 378                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 379                         reg-shift = <2>;
 380                         reg-io-width = <4>;
 381                         clocks = <&ccu CLK_BUS_UART2>;
 382                         resets = <&ccu RST_BUS_UART2>;
 383                         status = "disabled";
 384                 };
 385
 386                 uart3: serial@5000c00 {
 387                         compatible = "snps,dw-apb-uart";
 388                         reg = <0x05000c00 0x400>;
 389                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 390                         reg-shift = <2>;
 391                         reg-io-width = <4>;
 392                         clocks = <&ccu CLK_BUS_UART3>;
 393                         resets = <&ccu RST_BUS_UART3>;
 394                         status = "disabled";
 395                 };
 396
 397                 emac: ethernet@5020000 {
 398                         compatible = "allwinner,sun50i-h6-emac",
 399                                      "allwinner,sun50i-a64-emac";
 400                         syscon = <&syscon>;
 401                         reg = <0x05020000 0x10000>;
 402                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 403                         interrupt-names = "macirq";
 404                         resets = <&ccu RST_BUS_EMAC>;
 405                         reset-names = "stmmaceth";
 406                         clocks = <&ccu CLK_BUS_EMAC>;
 407                         clock-names = "stmmaceth";
 408                         status = "disabled";
 409
 410                         mdio: mdio {
 411                                 compatible = "snps,dwmac-mdio";
 412                                 #address-cells = <1>;
 413                                 #size-cells = <0>;
 414                         };
 415                 };
 416
 417                 usb2otg: usb@5100000 {
 418                         compatible = "allwinner,sun50i-h6-musb",
 419                                      "allwinner,sun8i-a33-musb";
 420                         reg = <0x05100000 0x0400>;
 421                         clocks = <&ccu CLK_BUS_OTG>;
 422                         resets = <&ccu RST_BUS_OTG>;
 423                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 424                         interrupt-names = "mc";
 425                         phys = <&usb2phy 0>;
 426                         phy-names = "usb";
 427                         extcon = <&usb2phy 0>;
 428                         status = "disabled";
 429                 };
 430
 431                 usb2phy: phy@5100400 {
 432                         compatible = "allwinner,sun50i-h6-usb-phy";
 433                         reg = <0x05100400 0x24>,
 434                               <0x05101800 0x4>,
 435                               <0x05311800 0x4>;
 436                         reg-names = "phy_ctrl",
 437                                     "pmu0",
 438                                     "pmu3";
 439                         clocks = <&ccu CLK_USB_PHY0>,
 440                                  <&ccu CLK_USB_PHY3>;
 441                         clock-names = "usb0_phy",
 442                                       "usb3_phy";
 443                         resets = <&ccu RST_USB_PHY0>,
 444                                  <&ccu RST_USB_PHY3>;
 445                         reset-names = "usb0_reset",
 446                                       "usb3_reset";
 447                         status = "disabled";
 448                         #phy-cells = <1>;
 449                 };
 450
 451                 ehci0: usb@5101000 {
 452                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 453                         reg = <0x05101000 0x100>;
 454                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&ccu CLK_BUS_OHCI0>,
 456                                  <&ccu CLK_BUS_EHCI0>,
 457                                  <&ccu CLK_USB_OHCI0>;
 458                         resets = <&ccu RST_BUS_OHCI0>,
 459                                  <&ccu RST_BUS_EHCI0>;
 460                         status = "disabled";
 461                 };
 462
 463                 ohci0: usb@5101400 {
 464                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 465                         reg = <0x05101400 0x100>;
 466                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 467                         clocks = <&ccu CLK_BUS_OHCI0>,
 468                                  <&ccu CLK_USB_OHCI0>;
 469                         resets = <&ccu RST_BUS_OHCI0>;
 470                         status = "disabled";
 471                 };
 472
 473                 ehci3: usb@5311000 {
 474                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 475                         reg = <0x05311000 0x100>;
 476                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 477                         clocks = <&ccu CLK_BUS_OHCI3>,
 478                                  <&ccu CLK_BUS_EHCI3>,
 479                                  <&ccu CLK_USB_OHCI3>;
 480                         resets = <&ccu RST_BUS_OHCI3>,
 481                                  <&ccu RST_BUS_EHCI3>;
 482                         phys = <&usb2phy 3>;
 483                         status = "disabled";
 484                 };
 485
 486                 ohci3: usb@5311400 {
 487                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 488                         reg = <0x05311400 0x100>;
 489                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&ccu CLK_BUS_OHCI3>,
 491                                  <&ccu CLK_USB_OHCI3>;
 492                         resets = <&ccu RST_BUS_OHCI3>;
 493                         phys = <&usb2phy 3>;
 494                         status = "disabled";
 495                 };
 496
 497                 hdmi: hdmi@6000000 {
 498                         compatible = "allwinner,sun50i-h6-dw-hdmi";
 499                         reg = <0x06000000 0x10000>;
 500                         reg-io-width = <1>;
 501                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 503                                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
 504                                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
 505                         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
 506                                       "hdcp-bus";
 507                         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
 508                         reset-names = "ctrl", "hdcp";
 509                         phys = <&hdmi_phy>;
 510                         phy-names = "hdmi-phy";
 511                         pinctrl-names = "default";
 512                         pinctrl-0 = <&hdmi_pins>;
 513                         status = "disabled";
 514
 515                         ports {
 516                                 #address-cells = <1>;
 517                                 #size-cells = <0>;
 518
 519                                 hdmi_in: port@0 {
 520                                         reg = <0>;
 521
 522                                         hdmi_in_tcon_top: endpoint {
 523                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 524                                         };
 525                                 };
 526
 527                                 hdmi_out: port@1 {
 528                                         reg = <1>;
 529                                 };
 530                         };
 531                 };
 532
 533                 hdmi_phy: hdmi-phy@6010000 {
 534                         compatible = "allwinner,sun50i-h6-hdmi-phy";
 535                         reg = <0x06010000 0x10000>;
 536                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 537                         clock-names = "bus", "mod";
 538                         resets = <&ccu RST_BUS_HDMI>;
 539                         reset-names = "phy";
 540                         #phy-cells = <0>;
 541                 };
 542
 543                 tcon_top: tcon-top@6510000 {
 544                         compatible = "allwinner,sun50i-h6-tcon-top";
 545                         reg = <0x06510000 0x1000>;
 546                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 547                                  <&ccu CLK_TCON_TV0>;
 548                         clock-names = "bus",
 549                                       "tcon-tv0";
 550                         clock-output-names = "tcon-top-tv0";
 551                         resets = <&ccu RST_BUS_TCON_TOP>;
 552                         reset-names = "rst";
 553                         #clock-cells = <1>;
 554
 555                         ports {
 556                                 #address-cells = <1>;
 557                                 #size-cells = <0>;
 558
 559                                 tcon_top_mixer0_in: port@0 {
 560                                         #address-cells = <1>;
 561                                         #size-cells = <0>;
 562                                         reg = <0>;
 563
 564                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
 565                                                 reg = <0>;
 566                                                 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
 567                                         };
 568                                 };
 569
 570                                 tcon_top_mixer0_out: port@1 {
 571                                         #address-cells = <1>;
 572                                         #size-cells = <0>;
 573                                         reg = <1>;
 574
 575                                         tcon_top_mixer0_out_tcon_tv: endpoint@2 {
 576                                                 reg = <2>;
 577                                                 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
 578                                         };
 579                                 };
 580
 581                                 tcon_top_hdmi_in: port@4 {
 582                                         #address-cells = <1>;
 583                                         #size-cells = <0>;
 584                                         reg = <4>;
 585
 586                                         tcon_top_hdmi_in_tcon_tv: endpoint@0 {
 587                                                 reg = <0>;
 588                                                 remote-endpoint = <&tcon_tv_out_tcon_top>;
 589                                         };
 590                                 };
 591
 592                                 tcon_top_hdmi_out: port@5 {
 593                                         reg = <5>;
 594
 595                                         tcon_top_hdmi_out_hdmi: endpoint {
 596                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 597                                         };
 598                                 };
 599                         };
 600                 };
 601
 602                 tcon_tv: lcd-controller@6515000 {
 603                         compatible = "allwinner,sun50i-h6-tcon-tv",
 604                                      "allwinner,sun8i-r40-tcon-tv";
 605                         reg = <0x06515000 0x1000>;
 606                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 607                         clocks = <&ccu CLK_BUS_TCON_TV0>,
 608                                  <&tcon_top CLK_TCON_TOP_TV0>;
 609                         clock-names = "ahb",
 610                                       "tcon-ch1";
 611                         resets = <&ccu RST_BUS_TCON_TV0>;
 612                         reset-names = "lcd";
 613
 614                         ports {
 615                                 #address-cells = <1>;
 616                                 #size-cells = <0>;
 617
 618                                 tcon_tv_in: port@0 {
 619                                         reg = <0>;
 620
 621                                         tcon_tv_in_tcon_top_mixer0: endpoint {
 622                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
 623                                         };
 624                                 };
 625
 626                                 tcon_tv_out: port@1 {
 627                                         #address-cells = <1>;
 628                                         #size-cells = <0>;
 629                                         reg = <1>;
 630
 631                                         tcon_tv_out_tcon_top: endpoint@1 {
 632                                                 reg = <1>;
 633                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
 634                                         };
 635                                 };
 636                         };
 637                 };
 638
 639                 r_ccu: clock@7010000 {
 640                         compatible = "allwinner,sun50i-h6-r-ccu";
 641                         reg = <0x07010000 0x400>;
 642                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 643                                  <&ccu CLK_PLL_PERIPH0>;
 644                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 645                         #clock-cells = <1>;
 646                         #reset-cells = <1>;
 647                 };
 648
 649                 r_watchdog: watchdog@7020400 {
 650                         compatible = "allwinner,sun50i-h6-wdt",
 651                                      "allwinner,sun6i-a31-wdt";
 652                         reg = <0x07020400 0x20>;
 653                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 654                 };
 655
 656                 r_intc: interrupt-controller@7021000 {
 657                         compatible = "allwinner,sun50i-h6-r-intc",
 658                                      "allwinner,sun6i-a31-r-intc";
 659                         interrupt-controller;
 660                         #interrupt-cells = <2>;
 661                         reg = <0x07021000 0x400>;
 662                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 663                 };
 664
 665                 r_pio: pinctrl@7022000 {
 666                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 667                         reg = <0x07022000 0x400>;
 668                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 670                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
 671                         clock-names = "apb", "hosc", "losc";
 672                         gpio-controller;
 673                         #gpio-cells = <3>;
 674                         interrupt-controller;
 675                         #interrupt-cells = <3>;
 676
 677                         r_i2c_pins: r-i2c-pins {
 678                                 pins = "PL0", "PL1";
 679                                 function = "s_i2c";
 680                         };
 681                 };
 682
 683                 r_i2c: i2c@7081400 {
 684                         compatible = "allwinner,sun6i-a31-i2c";
 685                         reg = <0x07081400 0x400>;
 686                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 687                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 688                         resets = <&r_ccu RST_R_APB2_I2C>;
 689                         pinctrl-names = "default";
 690                         pinctrl-0 = <&r_i2c_pins>;
 691                         status = "disabled";
 692                         #address-cells = <1>;
 693                         #size-cells = <0>;
 694                 };
 695         };
 696 };