arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  13
  14 / {
  15         u-boot,dm-pre-reloc;
  16         config {
  17                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  18         };
  19 };
  20
  21 &i2c4 {
  22         u-boot,dm-pre-reloc;
  23 };
  24
  25 &i2c4_pins_a {
  26         u-boot,dm-pre-reloc;
  27         pins {
  28                 u-boot,dm-pre-reloc;
  29         };
  30 };
  31
  32 &pmic {
  33         u-boot,dm-pre-reloc;
  34 };
  35
  36 &qspi {
  37         u-boot,dm-spl;
  38 };
  39
  40 &rcc {
  41         st,clksrc = <
  42                 CLK_MPU_PLL1P
  43                 CLK_AXI_PLL2P
  44                 CLK_MCU_PLL3P
  45                 CLK_PLL12_HSE
  46                 CLK_PLL3_HSE
  47                 CLK_PLL4_HSE
  48                 CLK_RTC_LSE
  49                 CLK_MCO1_DISABLED
  50                 CLK_MCO2_DISABLED
  51         >;
  52
  53         st,clkdiv = <
  54                 1 /*MPU*/
  55                 0 /*AXI*/
  56                 0 /*MCU*/
  57                 1 /*APB1*/
  58                 1 /*APB2*/
  59                 1 /*APB3*/
  60                 1 /*APB4*/
  61                 2 /*APB5*/
  62                 23 /*RTC*/
  63                 0 /*MCO1*/
  64                 0 /*MCO2*/
  65         >;
  66
  67         st,pkcs = <
  68                 CLK_CKPER_HSE
  69                 CLK_FMC_ACLK
  70                 CLK_QSPI_ACLK
  71                 CLK_ETH_DISABLED
  72                 CLK_SDMMC12_PLL4P
  73                 CLK_DSI_DSIPLL
  74                 CLK_STGEN_HSE
  75                 CLK_USBPHY_HSE
  76                 CLK_SPI2S1_PLL3Q
  77                 CLK_SPI2S23_PLL3Q
  78                 CLK_SPI45_HSI
  79                 CLK_SPI6_HSI
  80                 CLK_I2C46_HSI
  81                 CLK_SDMMC3_PLL4P
  82                 CLK_USBO_USBPHY
  83                 CLK_ADC_CKPER
  84                 CLK_CEC_LSE
  85                 CLK_I2C12_HSI
  86                 CLK_I2C35_HSI
  87                 CLK_UART1_HSI
  88                 CLK_UART24_HSI
  89                 CLK_UART35_HSI
  90                 CLK_UART6_HSI
  91                 CLK_UART78_HSI
  92                 CLK_SPDIF_PLL4P
  93                 CLK_FDCAN_PLL4R
  94                 CLK_SAI1_PLL3Q
  95                 CLK_SAI2_PLL3Q
  96                 CLK_SAI3_PLL3Q
  97                 CLK_SAI4_PLL3Q
  98                 CLK_RNG1_LSI
  99                 CLK_RNG2_LSI
 100                 CLK_LPTIM1_PCLK1
 101                 CLK_LPTIM23_PCLK3
 102                 CLK_LPTIM45_LSE
 103         >;
 104
 105         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 106         pll1: st,pll@0 {
 107                 compatible = "st,stm32mp1-pll";
 108                 reg = <0>;
 109                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 110                 frac = < 0x800 >;
 111                 u-boot,dm-pre-reloc;
 112         };
 113
 114         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 115         pll2: st,pll@1 {
 116                 compatible = "st,stm32mp1-pll";
 117                 reg = <1>;
 118                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 119                 frac = < 0x1400 >;
 120                 u-boot,dm-pre-reloc;
 121         };
 122
 123         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 124         pll3: st,pll@2 {
 125                 compatible = "st,stm32mp1-pll";
 126                 reg = <2>;
 127                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 128                 frac = < 0x1a04 >;
 129                 u-boot,dm-pre-reloc;
 130         };
 131
 132         /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
 133         pll4: st,pll@3 {
 134                 compatible = "st,stm32mp1-pll";
 135                 reg = <3>;
 136                 cfg = < 1 49 5 11 5 PQR(1,1,1) >;
 137                 u-boot,dm-pre-reloc;
 138         };
 139 };