arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  *
   5  * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
   6  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
   8  */
   9
  10 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  11 #include "stm32mp15-u-boot.dtsi"
  12 #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
  13 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  14
  15 / {
  16         u-boot,dm-pre-reloc;
  17         config {
  18                 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  19                 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  20         };
  21 };
  22
  23 &i2c4 {
  24         u-boot,dm-pre-reloc;
  25 };
  26
  27 &i2c4_pins_a {
  28         u-boot,dm-pre-reloc;
  29         pins {
  30                 u-boot,dm-pre-reloc;
  31         };
  32 };
  33
  34 &pmic {
  35         u-boot,dm-pre-reloc;
  36 };
  37
  38 &qspi {
  39         u-boot,dm-spl;
  40 };
  41
  42 &rcc {
  43         st,clksrc = <
  44                 CLK_MPU_PLL1P
  45                 CLK_AXI_PLL2P
  46                 CLK_MCU_PLL3P
  47                 CLK_PLL12_HSE
  48                 CLK_PLL3_HSE
  49                 CLK_PLL4_HSE
  50                 CLK_RTC_LSE
  51                 CLK_MCO1_DISABLED
  52                 CLK_MCO2_DISABLED
  53         >;
  54
  55         st,clkdiv = <
  56                 1 /*MPU*/
  57                 0 /*AXI*/
  58                 0 /*MCU*/
  59                 1 /*APB1*/
  60                 1 /*APB2*/
  61                 1 /*APB3*/
  62                 1 /*APB4*/
  63                 2 /*APB5*/
  64                 23 /*RTC*/
  65                 0 /*MCO1*/
  66                 0 /*MCO2*/
  67         >;
  68
  69         st,pkcs = <
  70                 CLK_CKPER_HSE
  71                 CLK_FMC_ACLK
  72                 CLK_QSPI_ACLK
  73                 CLK_ETH_DISABLED
  74                 CLK_SDMMC12_PLL4P
  75                 CLK_DSI_DSIPLL
  76                 CLK_STGEN_HSE
  77                 CLK_USBPHY_HSE
  78                 CLK_SPI2S1_PLL3Q
  79                 CLK_SPI2S23_PLL3Q
  80                 CLK_SPI45_HSI
  81                 CLK_SPI6_HSI
  82                 CLK_I2C46_HSI
  83                 CLK_SDMMC3_PLL4P
  84                 CLK_USBO_USBPHY
  85                 CLK_ADC_CKPER
  86                 CLK_CEC_LSE
  87                 CLK_I2C12_HSI
  88                 CLK_I2C35_HSI
  89                 CLK_UART1_HSI
  90                 CLK_UART24_HSI
  91                 CLK_UART35_HSI
  92                 CLK_UART6_HSI
  93                 CLK_UART78_HSI
  94                 CLK_SPDIF_PLL4P
  95                 CLK_FDCAN_PLL4R
  96                 CLK_SAI1_PLL3Q
  97                 CLK_SAI2_PLL3Q
  98                 CLK_SAI3_PLL3Q
  99                 CLK_SAI4_PLL3Q
 100                 CLK_RNG1_LSI
 101                 CLK_RNG2_LSI
 102                 CLK_LPTIM1_PCLK1
 103                 CLK_LPTIM23_PCLK3
 104                 CLK_LPTIM45_LSE
 105         >;
 106
 107         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 108         pll1: st,pll@0 {
 109                 compatible = "st,stm32mp1-pll";
 110                 reg = <0>;
 111                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 112                 frac = < 0x800 >;
 113                 u-boot,dm-pre-reloc;
 114         };
 115
 116         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 117         pll2: st,pll@1 {
 118                 compatible = "st,stm32mp1-pll";
 119                 reg = <1>;
 120                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 121                 frac = < 0x1400 >;
 122                 u-boot,dm-pre-reloc;
 123         };
 124
 125         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 126         pll3: st,pll@2 {
 127                 compatible = "st,stm32mp1-pll";
 128                 reg = <2>;
 129                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 130                 frac = < 0x1a04 >;
 131                 u-boot,dm-pre-reloc;
 132         };
 133
 134         /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
 135         pll4: st,pll@3 {
 136                 compatible = "st,stm32mp1-pll";
 137                 reg = <3>;
 138                 cfg = < 1 49 5 11 5 PQR(1,1,1) >;
 139                 u-boot,dm-pre-reloc;
 140         };
 141 };