arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c3 = &i2c4;
  13                 mmc0 = &sdmmc1;
  14                 mmc1 = &sdmmc2;
  15         };
  16
  17         config {
  18                 u-boot,boot-led = "heartbeat";
  19                 u-boot,error-led = "error";
  20                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  21                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  22         };
  23
  24         firmware {
  25                 optee {
  26                         compatible = "linaro,optee-tz";
  27                         method = "smc";
  28                 };
  29         };
  30
  31         reserved-memory {
  32                 optee@fe000000 {
  33                         reg = <0xfe000000 0x02000000>;
  34                         no-map;
  35                 };
  36         };
  37
  38         led {
  39                 red {
  40                         label = "error";
  41                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  42                         default-state = "off";
  43                         status = "okay";
  44                 };
  45         };
  46 };
  47
  48 &clk_hse {
  49         st,digbypass;
  50 };
  51
  52 &i2c4 {
  53         u-boot,dm-pre-reloc;
  54 };
  55
  56 &i2c4_pins_a {
  57         u-boot,dm-pre-reloc;
  58         pins {
  59                 u-boot,dm-pre-reloc;
  60         };
  61 };
  62
  63 &pmic {
  64         u-boot,dm-pre-reloc;
  65 };
  66
  67 &rcc {
  68         st,clksrc = <
  69                 CLK_MPU_PLL1P
  70                 CLK_AXI_PLL2P
  71                 CLK_MCU_PLL3P
  72                 CLK_PLL12_HSE
  73                 CLK_PLL3_HSE
  74                 CLK_PLL4_HSE
  75                 CLK_RTC_LSE
  76                 CLK_MCO1_DISABLED
  77                 CLK_MCO2_DISABLED
  78         >;
  79
  80         st,clkdiv = <
  81                 1 /*MPU*/
  82                 0 /*AXI*/
  83                 0 /*MCU*/
  84                 1 /*APB1*/
  85                 1 /*APB2*/
  86                 1 /*APB3*/
  87                 1 /*APB4*/
  88                 2 /*APB5*/
  89                 23 /*RTC*/
  90                 0 /*MCO1*/
  91                 0 /*MCO2*/
  92         >;
  93
  94         st,pkcs = <
  95                 CLK_CKPER_HSE
  96                 CLK_FMC_ACLK
  97                 CLK_QSPI_ACLK
  98                 CLK_ETH_DISABLED
  99                 CLK_SDMMC12_PLL4P
 100                 CLK_DSI_DSIPLL
 101                 CLK_STGEN_HSE
 102                 CLK_USBPHY_HSE
 103                 CLK_SPI2S1_PLL3Q
 104                 CLK_SPI2S23_PLL3Q
 105                 CLK_SPI45_HSI
 106                 CLK_SPI6_HSI
 107                 CLK_I2C46_HSI
 108                 CLK_SDMMC3_PLL4P
 109                 CLK_USBO_USBPHY
 110                 CLK_ADC_CKPER
 111                 CLK_CEC_LSE
 112                 CLK_I2C12_HSI
 113                 CLK_I2C35_HSI
 114                 CLK_UART1_HSI
 115                 CLK_UART24_HSI
 116                 CLK_UART35_HSI
 117                 CLK_UART6_HSI
 118                 CLK_UART78_HSI
 119                 CLK_SPDIF_PLL4P
 120                 CLK_FDCAN_PLL4R
 121                 CLK_SAI1_PLL3Q
 122                 CLK_SAI2_PLL3Q
 123                 CLK_SAI3_PLL3Q
 124                 CLK_SAI4_PLL3Q
 125                 CLK_RNG1_LSI
 126                 CLK_RNG2_LSI
 127                 CLK_LPTIM1_PCLK1
 128                 CLK_LPTIM23_PCLK3
 129                 CLK_LPTIM45_LSE
 130         >;
 131
 132         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 133         pll1: st,pll@0 {
 134                 compatible = "st,stm32mp1-pll";
 135                 reg = <0>;
 136                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 137                 frac = < 0x800 >;
 138                 u-boot,dm-pre-reloc;
 139         };
 140
 141         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 142         pll2: st,pll@1 {
 143                 compatible = "st,stm32mp1-pll";
 144                 reg = <1>;
 145                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 146                 frac = < 0x1400 >;
 147                 u-boot,dm-pre-reloc;
 148         };
 149
 150         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 151         pll3: st,pll@2 {
 152                 compatible = "st,stm32mp1-pll";
 153                 reg = <2>;
 154                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 155                 frac = < 0x1a04 >;
 156                 u-boot,dm-pre-reloc;
 157         };
 158
 159         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 160         pll4: st,pll@3 {
 161                 compatible = "st,stm32mp1-pll";
 162                 reg = <3>;
 163                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 164                 u-boot,dm-pre-reloc;
 165         };
 166 };
 167
 168 &sdmmc1 {
 169         u-boot,dm-spl;
 170         broken-cd;
 171         /delete-property/ cd-gpios;
 172 };
 173
 174 &sdmmc1_b4_pins_a {
 175         u-boot,dm-spl;
 176         pins1 {
 177                 u-boot,dm-spl;
 178         };
 179         pins2 {
 180                 u-boot,dm-spl;
 181         };
 182 };
 183
 184 &sdmmc1_dir_pins_a {
 185         u-boot,dm-spl;
 186         pins1 {
 187                 u-boot,dm-spl;
 188         };
 189         pins2 {
 190                 u-boot,dm-spl;
 191         };
 192 };
 193
 194 &sdmmc2 {
 195         u-boot,dm-spl;
 196 };
 197
 198 &sdmmc2_b4_pins_a {
 199         u-boot,dm-spl;
 200         pins1 {
 201                 u-boot,dm-spl;
 202         };
 203         pins2 {
 204                 u-boot,dm-spl;
 205         };
 206 };
 207
 208 &sdmmc2_d47_pins_a {
 209         u-boot,dm-spl;
 210         pins {
 211                 u-boot,dm-spl;
 212         };
 213 };
 214
 215 &uart4 {
 216         u-boot,dm-pre-reloc;
 217 };
 218
 219 &uart4_pins_a {
 220         u-boot,dm-pre-reloc;
 221         pins1 {
 222                 u-boot,dm-pre-reloc;
 223         };
 224         pins2 {
 225                 u-boot,dm-pre-reloc;
 226                 /* pull-up on rx to avoid floating level */
 227                 bias-pull-up;
 228         };
 229 };