arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c3 = &i2c4;
  13                 mmc0 = &sdmmc1;
  14                 usb0 = &usbotg_hs;
  15         };
  16         config {
  17                 u-boot,boot-led = "heartbeat";
  18                 u-boot,error-led = "error";
  19                 st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
  20                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  21                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  22         };
  23
  24         firmware {
  25                 optee {
  26                         compatible = "linaro,optee-tz";
  27                         method = "smc";
  28                 };
  29         };
  30
  31         reserved-memory {
  32                 optee@de000000 {
  33                         reg = <0xde000000 0x02000000>;
  34                         no-map;
  35                 };
  36         };
  37
  38         led {
  39                 red {
  40                         label = "error";
  41                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  42                         default-state = "off";
  43                         status = "okay";
  44                 };
  45         };
  46 };
  47
  48 &adc {
  49         status = "okay";
  50 };
  51
  52 &clk_hse {
  53         st,digbypass;
  54 };
  55
  56 &i2c4 {
  57         u-boot,dm-pre-reloc;
  58 };
  59
  60 &i2c4_pins_a {
  61         u-boot,dm-pre-reloc;
  62         pins {
  63                 u-boot,dm-pre-reloc;
  64         };
  65 };
  66
  67 &pmic {
  68         u-boot,dm-pre-reloc;
  69 };
  70
  71 &rcc {
  72         st,clksrc = <
  73                 CLK_MPU_PLL1P
  74                 CLK_AXI_PLL2P
  75                 CLK_MCU_PLL3P
  76                 CLK_PLL12_HSE
  77                 CLK_PLL3_HSE
  78                 CLK_PLL4_HSE
  79                 CLK_RTC_LSE
  80                 CLK_MCO1_DISABLED
  81                 CLK_MCO2_DISABLED
  82         >;
  83
  84         st,clkdiv = <
  85                 1 /*MPU*/
  86                 0 /*AXI*/
  87                 0 /*MCU*/
  88                 1 /*APB1*/
  89                 1 /*APB2*/
  90                 1 /*APB3*/
  91                 1 /*APB4*/
  92                 2 /*APB5*/
  93                 23 /*RTC*/
  94                 0 /*MCO1*/
  95                 0 /*MCO2*/
  96         >;
  97
  98         st,pkcs = <
  99                 CLK_CKPER_HSE
 100                 CLK_FMC_ACLK
 101                 CLK_QSPI_ACLK
 102                 CLK_ETH_DISABLED
 103                 CLK_SDMMC12_PLL4P
 104                 CLK_DSI_DSIPLL
 105                 CLK_STGEN_HSE
 106                 CLK_USBPHY_HSE
 107                 CLK_SPI2S1_PLL3Q
 108                 CLK_SPI2S23_PLL3Q
 109                 CLK_SPI45_HSI
 110                 CLK_SPI6_HSI
 111                 CLK_I2C46_HSI
 112                 CLK_SDMMC3_PLL4P
 113                 CLK_USBO_USBPHY
 114                 CLK_ADC_CKPER
 115                 CLK_CEC_LSE
 116                 CLK_I2C12_HSI
 117                 CLK_I2C35_HSI
 118                 CLK_UART1_HSI
 119                 CLK_UART24_HSI
 120                 CLK_UART35_HSI
 121                 CLK_UART6_HSI
 122                 CLK_UART78_HSI
 123                 CLK_SPDIF_PLL4P
 124                 CLK_FDCAN_PLL4R
 125                 CLK_SAI1_PLL3Q
 126                 CLK_SAI2_PLL3Q
 127                 CLK_SAI3_PLL3Q
 128                 CLK_SAI4_PLL3Q
 129                 CLK_RNG1_LSI
 130                 CLK_RNG2_LSI
 131                 CLK_LPTIM1_PCLK1
 132                 CLK_LPTIM23_PCLK3
 133                 CLK_LPTIM45_LSE
 134         >;
 135
 136         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 137         pll1: st,pll@0 {
 138                 compatible = "st,stm32mp1-pll";
 139                 reg = <0>;
 140                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 141                 frac = < 0x800 >;
 142                 u-boot,dm-pre-reloc;
 143         };
 144
 145         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 146         pll2: st,pll@1 {
 147                 compatible = "st,stm32mp1-pll";
 148                 reg = <1>;
 149                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 150                 frac = < 0x1400 >;
 151                 u-boot,dm-pre-reloc;
 152         };
 153
 154         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 155         pll3: st,pll@2 {
 156                 compatible = "st,stm32mp1-pll";
 157                 reg = <2>;
 158                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 159                 frac = < 0x1a04 >;
 160                 u-boot,dm-pre-reloc;
 161         };
 162
 163         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 164         pll4: st,pll@3 {
 165                 compatible = "st,stm32mp1-pll";
 166                 reg = <3>;
 167                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 168                 u-boot,dm-pre-reloc;
 169         };
 170 };
 171
 172 &sdmmc1 {
 173         u-boot,dm-spl;
 174 };
 175
 176 &sdmmc1_b4_pins_a {
 177         u-boot,dm-spl;
 178         pins1 {
 179                 u-boot,dm-spl;
 180         };
 181         pins2 {
 182                 u-boot,dm-spl;
 183         };
 184 };
 185
 186 &uart4 {
 187         u-boot,dm-pre-reloc;
 188 };
 189
 190 &uart4_pins_a {
 191         u-boot,dm-pre-reloc;
 192         pins1 {
 193                 u-boot,dm-pre-reloc;
 194         };
 195         pins2 {
 196                 u-boot,dm-pre-reloc;
 197                 /* pull-up on rx to avoid floating level */
 198                 bias-pull-up;
 199         };
 200 };
 201
 202 &usbotg_hs {
 203         u-boot,force-b-session-valid;
 204         hnp-srp-disable;
 205 };