arch/arm/dts/socfpga_agilex-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * U-Boot additions
   4  *
   5  * Copyright (C) 2019 Intel Corporation <www.intel.com>
   6  */
   7
   8 /{
   9         memory {
  10                 #address-cells = <2>;
  11                 #size-cells = <2>;
  12                 u-boot,dm-pre-reloc;
  13         };
  14
  15         soc {
  16                 u-boot,dm-pre-reloc;
  17
  18                 ccu: cache-controller@f7000000 {
  19                         compatible = "arteris,ncore-ccu";
  20                         reg = <0xf7000000 0x100900>;
  21                         u-boot,dm-pre-reloc;
  22                 };
  23         };
  24 };
  25
  26 &clkmgr {
  27         u-boot,dm-pre-reloc;
  28 };
  29
  30 &gmac1 {
  31         altr,sysmgr-syscon = <&sysmgr 0x48 0>;
  32 };
  33
  34 &gmac2 {
  35         altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
  36 };
  37
  38 &i2c0 {
  39         reset-names = "i2c";
  40 };
  41
  42 &i2c1 {
  43         reset-names = "i2c";
  44 };
  45
  46 &i2c2 {
  47         reset-names = "i2c";
  48 };
  49
  50 &i2c3 {
  51         reset-names = "i2c";
  52 };
  53
  54 &mmc {
  55         resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
  56 };
  57
  58 &porta {
  59         bank-name = "porta";
  60 };
  61
  62 &portb {
  63         bank-name = "portb";
  64 };
  65
  66 &qspi {
  67         u-boot,dm-pre-reloc;
  68 };
  69
  70 &rst {
  71         compatible = "altr,rst-mgr";
  72         altr,modrst-offset = <0x20>;
  73         u-boot,dm-pre-reloc;
  74 };
  75
  76 &sdr {
  77         compatible = "intel,sdr-ctl-agilex";
  78         reg = <0xf8000400 0x80>,
  79               <0xf8010000 0x190>,
  80               <0xf8011000 0x500>;
  81         resets = <&rst DDRSCH_RESET>;
  82         u-boot,dm-pre-reloc;
  83 };
  84
  85 &sysmgr {
  86         compatible = "altr,sys-mgr", "syscon";
  87         u-boot,dm-pre-reloc;
  88 };
  89
  90 &uart0 {
  91         u-boot,dm-pre-reloc;
  92 };
  93
  94 &watchdog0 {
  95         u-boot,dm-pre-reloc;
  96 };