arch/arm/dts/sam9x60.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
   4  *
   5  * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/dma/at91.h>
  12 #include <dt-bindings/pinctrl/at91.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/clock/at91.h>
  16
  17 /{
  18         model = "Microchip SAM9X60 SoC";
  19         compatible = "microchip,sam9x60";
  20
  21         aliases {
  22                 serial0 = &dbgu;
  23                 gpio0 = &pioA;
  24                 gpio1 = &pioB;
  25         };
  26
  27         clocks {
  28                 slow_xtal: slow_xtal {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                         clock-frequency = <0>;
  32                 };
  33
  34                 main_xtal: main_xtal {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <0>;
  38                 };
  39         };
  40
  41         ahb {
  42                 compatible = "simple-bus";
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 ranges;
  46
  47                 sdhci0: sdhci-host@80000000 {
  48                         compatible = "microchip,sam9x60-sdhci";
  49                         reg = <0x80000000 0x300>;
  50                         clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
  51                         clock-names = "hclock", "multclk", "baseclk";
  52                         bus-width = <4>;
  53                         pinctrl-names = "default";
  54                         pinctrl-0 = <&pinctrl_sdhci0>;
  55                 };
  56
  57                 apb {
  58                         compatible = "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges;
  62
  63                         macb0: ethernet@f802c000 {
  64                                 compatible = "cdns,sam9x60-macb", "cdns,macb";
  65                                 reg = <0xf802c000 0x100>;
  66                                 pinctrl-names = "default";
  67                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
  68                                 clock-names = "hclk", "pclk";
  69                                 clocks = <&macb0_clk>, <&macb0_clk>;
  70                                 status = "disabled";
  71                         };
  72
  73                         dbgu: serial@fffff200 {
  74                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
  75                                 reg = <0xfffff200 0x200>;
  76                                 pinctrl-names = "default";
  77                                 pinctrl-0 = <&pinctrl_dbgu>;
  78                                 clocks = <&dbgu_clk>;
  79                                 clock-names = "usart";
  80                         };
  81
  82                         pinctrl {
  83                                 #address-cells = <1>;
  84                                 #size-cells = <1>;
  85                                 compatible = "microchip,sam9x60-pinctrl", "simple-bus";
  86                                 ranges = <0xfffff400 0xfffff400 0x800>;
  87                                 reg = <0xfffff400 0x200         /* pioA */
  88                                        0xfffff600 0x200         /* pioB */
  89                                        0xfffff800 0x200         /* pioC */
  90                                        0xfffffa00 0x200>;       /* pioD */
  91
  92                                 /* shared pinctrl settings */
  93                                 dbgu {
  94                                         pinctrl_dbgu: dbgu-0 {
  95                                                 atmel,pins =
  96                                                         <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
  97                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  98                                         };
  99                                 };
 100
 101                                 macb0 {
 102                                         pinctrl_macb0_rmii: macb0_rmii-0 {
 103                                                 atmel,pins =
 104                                                         <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
 105                                                          AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
 106                                                          AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
 107                                                          AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
 108                                                          AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
 109                                                          AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
 110                                                          AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
 111                                                          AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
 112                                                          AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
 113                                                          AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
 114                                         };
 115                                 };
 116
 117                                 sdhci0 {
 118                                         pinctrl_sdhci0: sdhci0 {
 119                                                 atmel,pins =
 120                                                         <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK  periph A with pullup */
 121                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA16 CMD periph A with pullup */
 122                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA15 DAT0 periph A */
 123                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA18 DAT1 periph A with pullup */
 124                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA19 DAT2 periph A with pullup */
 125                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;              /* PA20 DAT3 periph A with pullup */
 126                                         };
 127                                 };
 128                         };
 129
 130                         pioA: gpio@fffff400 {
 131                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 132                                 reg = <0xfffff400 0x200>;
 133                                 #gpio-cells = <2>;
 134                                 gpio-controller;
 135                                 clocks = <&pioA_clk>;
 136                         };
 137
 138                         pioB: gpio@fffff600 {
 139                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 140                                 reg = <0xfffff600 0x200>;
 141                                 #gpio-cells = <2>;
 142                                 gpio-controller;
 143                                 clocks = <&pioB_clk>;
 144                         };
 145
 146                         pmc: pmc@fffffc00 {
 147                                 compatible = "atmel,at91sam9x5-pmc";
 148                                 reg = <0xfffffc00 0x200>;
 149                                 #address-cells = <1>;
 150                                 #size-cells = <0>;
 151
 152                                 main: mainck {
 153                                         compatible = "atmel,at91sam9x5-clk-main";
 154                                         #clock-cells = <0>;
 155                                 };
 156
 157                                 plla: pllack {
 158                                         compatible = "microchip,sam9x60-clk-pll";
 159                                         #clock-cells = <0>;
 160                                         clocks = <&main>;
 161                                         reg = <0>;
 162                                         atmel,clk-input-range = <8000000 24000000>;
 163                                         #atmel,pll-clk-output-range-cells = <4>;
 164                                         atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
 165                                 };
 166
 167                                 mck: masterck {
 168                                         compatible = "atmel,at91sam9x5-clk-master";
 169                                         #clock-cells = <0>;
 170                                         clocks = <&md_slck>, <&main>, <&plla>;
 171                                         atmel,clk-output-range = <140000000 200000000>;
 172                                         atmel,clk-divisors = <1 2 4 6>;
 173                                 };
 174
 175                                 periph: periphck {
 176                                         compatible = "microchip,sam9x60-clk-peripheral";
 177                                         #address-cells = <1>;
 178                                         #size-cells = <0>;
 179                                         clocks = <&mck>;
 180
 181                                         pioA_clk: pioA_clk {
 182                                                 #clock-cells = <0>;
 183                                                 reg = <2>;
 184                                         };
 185
 186                                         pioB_clk: pioB_clk {
 187                                                 #clock-cells = <0>;
 188                                                 reg = <3>;
 189                                         };
 190
 191                                         sdhci0_clk: sdhci0_clk {
 192                                                 #clock-cells = <0>;
 193                                                 reg = <12>;
 194                                         };
 195
 196                                         dbgu_clk: dbgu_clk {
 197                                                 #clock-cells = <0>;
 198                                                 reg = <47>;
 199                                         };
 200
 201                                         macb0_clk: macb0_clk {
 202                                                 #clock-cells = <0>;
 203                                                 reg = <24>;
 204                                         };
 205                                 };
 206
 207                                 generic: gck {
 208                                         compatible = "microchip,sam9x60-clk-generated";
 209                                         #address-cells = <1>;
 210                                         #size-cells = <0>;
 211                                         clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
 212
 213                                         sdhci0_gclk: sdhci0_gclk {
 214                                                 #clock-cells = <0>;
 215                                                 reg = <12>;
 216                                         };
 217                                 };
 218                         };
 219
 220                         pit: timer@fffffe40 {
 221                                 compatible = "atmel,at91sam9260-pit";
 222                                 reg = <0xfffffe40 0x10>;
 223                                 clocks = <&mck>;
 224                         };
 225
 226                         slowckc: sckc@fffffe50 {
 227                                 compatible = "atmel,at91sam9x5-sckc";
 228                                 reg = <0xfffffe50 0x4>;
 229
 230                                 slow_osc: slow_osc {
 231                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 232                                         #clock-cells = <0>;
 233                                         clocks = <&slow_xtal>;
 234                                 };
 235
 236                                 slow_rc_osc: slow_rc_osc {
 237                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 238                                         #clock-cells = <0>;
 239                                         clock-frequency = <32768>;
 240                                 };
 241
 242                                 td_slck: td_slck {
 243                                         compatible = "atmel,at91sam9x5-clk-slow";
 244                                         #clock-cells = <0>;
 245                                         clocks = <&slow_rc_osc>, <&slow_osc>;
 246                                 };
 247
 248                                 md_slck: md_slck {
 249                                         compatible = "atmel,at91sam9x5-clk-slow";
 250                                         #clock-cells = <0>;
 251                                         clocks = <&slow_rc_osc>;
 252                                 };
 253                         };
 254                 };
 255         };
 256 };