arch/arm/dts/rk3399.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 i2c6 = &i2c6;
  29                 i2c7 = &i2c7;
  30                 i2c8 = &i2c8;
  31                 serial0 = &uart0;
  32                 serial1 = &uart1;
  33                 serial2 = &uart2;
  34                 serial3 = &uart3;
  35                 serial4 = &uart4;
  36         };
  37
  38         cpus {
  39                 #address-cells = <2>;
  40                 #size-cells = <0>;
  41
  42                 cpu-map {
  43                         cluster0 {
  44                                 core0 {
  45                                         cpu = <&cpu_l0>;
  46                                 };
  47                                 core1 {
  48                                         cpu = <&cpu_l1>;
  49                                 };
  50                                 core2 {
  51                                         cpu = <&cpu_l2>;
  52                                 };
  53                                 core3 {
  54                                         cpu = <&cpu_l3>;
  55                                 };
  56                         };
  57
  58                         cluster1 {
  59                                 core0 {
  60                                         cpu = <&cpu_b0>;
  61                                 };
  62                                 core1 {
  63                                         cpu = <&cpu_b1>;
  64                                 };
  65                         };
  66                 };
  67
  68                 cpu_l0: cpu@0 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53", "arm,armv8";
  71                         reg = <0x0 0x0>;
  72                         enable-method = "psci";
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clocks = <&cru ARMCLKL>;
  75                 };
  76
  77                 cpu_l1: cpu@1 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53", "arm,armv8";
  80                         reg = <0x0 0x1>;
  81                         enable-method = "psci";
  82                         clocks = <&cru ARMCLKL>;
  83                 };
  84
  85                 cpu_l2: cpu@2 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53", "arm,armv8";
  88                         reg = <0x0 0x2>;
  89                         enable-method = "psci";
  90                         clocks = <&cru ARMCLKL>;
  91                 };
  92
  93                 cpu_l3: cpu@3 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x3>;
  97                         enable-method = "psci";
  98                         clocks = <&cru ARMCLKL>;
  99                 };
 100
 101                 cpu_b0: cpu@100 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a72", "arm,armv8";
 104                         reg = <0x0 0x100>;
 105                         enable-method = "psci";
 106                         #cooling-cells = <2>; /* min followed by max */
 107                         clocks = <&cru ARMCLKB>;
 108                 };
 109
 110                 cpu_b1: cpu@101 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a72", "arm,armv8";
 113                         reg = <0x0 0x101>;
 114                         enable-method = "psci";
 115                         clocks = <&cru ARMCLKB>;
 116                 };
 117         };
 118
 119         pmu_a53 {
 120                 compatible = "arm,cortex-a53-pmu";
 121                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 122         };
 123
 124         pmu_a72 {
 125                 compatible = "arm,cortex-a72-pmu";
 126                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 127         };
 128
 129         psci {
 130                 compatible = "arm,psci-1.0";
 131                 method = "smc";
 132         };
 133
 134         timer {
 135                 compatible = "arm,armv8-timer";
 136                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 137                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 138                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 139                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 140                 arm,no-tick-in-suspend;
 141         };
 142
 143         xin24m: xin24m {
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <24000000>;
 146                 clock-output-names = "xin24m";
 147                 #clock-cells = <0>;
 148         };
 149
 150         amba {
 151                 compatible = "simple-bus";
 152                 #address-cells = <2>;
 153                 #size-cells = <2>;
 154                 ranges;
 155
 156                 dmac_bus: dma-controller@ff6d0000 {
 157                         compatible = "arm,pl330", "arm,primecell";
 158                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 159                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 160                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 161                         #dma-cells = <1>;
 162                         clocks = <&cru ACLK_DMAC0_PERILP>;
 163                         clock-names = "apb_pclk";
 164                 };
 165
 166                 dmac_peri: dma-controller@ff6e0000 {
 167                         compatible = "arm,pl330", "arm,primecell";
 168                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 169                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 170                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 171                         #dma-cells = <1>;
 172                         clocks = <&cru ACLK_DMAC1_PERILP>;
 173                         clock-names = "apb_pclk";
 174                 };
 175         };
 176
 177         pcie0: pcie@f8000000 {
 178                 compatible = "rockchip,rk3399-pcie";
 179                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 180                       <0x0 0xfd000000 0x0 0x1000000>;
 181                 reg-names = "axi-base", "apb-base";
 182                 #address-cells = <3>;
 183                 #size-cells = <2>;
 184                 #interrupt-cells = <1>;
 185                 aspm-no-l0s;
 186                 bus-range = <0x0 0x1>;
 187                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 188                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 189                 clock-names = "aclk", "aclk-perf",
 190                               "hclk", "pm";
 191                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 192                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 193                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 194                 interrupt-names = "sys", "legacy", "client";
 195                 interrupt-map-mask = <0 0 0 7>;
 196                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 197                                 <0 0 0 2 &pcie0_intc 1>,
 198                                 <0 0 0 3 &pcie0_intc 2>,
 199                                 <0 0 0 4 &pcie0_intc 3>;
 200                 linux,pci-domain = <0>;
 201                 max-link-speed = <1>;
 202                 msi-map = <0x0 &its 0x0 0x1000>;
 203                 phys = <&pcie_phy>;
 204                 phy-names = "pcie-phy";
 205                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
 206                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
 207                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 208                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 209                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 210                          <&cru SRST_A_PCIE>;
 211                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 212                               "pm", "pclk", "aclk";
 213                 status = "disabled";
 214
 215                 pcie0_intc: interrupt-controller {
 216                         interrupt-controller;
 217                         #address-cells = <0>;
 218                         #interrupt-cells = <1>;
 219                 };
 220         };
 221
 222         gmac: ethernet@fe300000 {
 223                 compatible = "rockchip,rk3399-gmac";
 224                 reg = <0x0 0xfe300000 0x0 0x10000>;
 225                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 226                 interrupt-names = "macirq";
 227                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 228                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 229                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 230                          <&cru PCLK_GMAC>;
 231                 clock-names = "stmmaceth", "mac_clk_rx",
 232                               "mac_clk_tx", "clk_mac_ref",
 233                               "clk_mac_refout", "aclk_mac",
 234                               "pclk_mac";
 235                 power-domains = <&power RK3399_PD_GMAC>;
 236                 resets = <&cru SRST_A_GMAC>;
 237                 reset-names = "stmmaceth";
 238                 rockchip,grf = <&grf>;
 239                 status = "disabled";
 240         };
 241
 242         sdio0: dwmmc@fe310000 {
 243                 compatible = "rockchip,rk3399-dw-mshc",
 244                              "rockchip,rk3288-dw-mshc";
 245                 reg = <0x0 0xfe310000 0x0 0x4000>;
 246                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 247                 max-frequency = <150000000>;
 248                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 249                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 250                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 251                 fifo-depth = <0x100>;
 252                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 253                 resets = <&cru SRST_SDIO0>;
 254                 reset-names = "reset";
 255                 status = "disabled";
 256         };
 257
 258         sdmmc: dwmmc@fe320000 {
 259                 compatible = "rockchip,rk3399-dw-mshc",
 260                              "rockchip,rk3288-dw-mshc";
 261                 reg = <0x0 0xfe320000 0x0 0x4000>;
 262                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 263                 max-frequency = <150000000>;
 264                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 265                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 266                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 267                 fifo-depth = <0x100>;
 268                 power-domains = <&power RK3399_PD_SD>;
 269                 resets = <&cru SRST_SDMMC>;
 270                 reset-names = "reset";
 271                 status = "disabled";
 272         };
 273
 274         sdhci: sdhci@fe330000 {
 275                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 276                 reg = <0x0 0xfe330000 0x0 0x10000>;
 277                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 278                 arasan,soc-ctl-syscon = <&grf>;
 279                 assigned-clocks = <&cru SCLK_EMMC>;
 280                 assigned-clock-rates = <200000000>;
 281                 max-frequency = <200000000>;
 282                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 283                 clock-names = "clk_xin", "clk_ahb";
 284                 clock-output-names = "emmc_cardclock";
 285                 #clock-cells = <0>;
 286                 phys = <&emmc_phy>;
 287                 phy-names = "phy_arasan";
 288                 power-domains = <&power RK3399_PD_EMMC>;
 289                 status = "disabled";
 290         };
 291
 292         usb_host0_ehci: usb@fe380000 {
 293                 compatible = "generic-ehci";
 294                 reg = <0x0 0xfe380000 0x0 0x20000>;
 295                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 296                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 297                          <&u2phy0>;
 298                 clock-names = "usbhost", "arbiter",
 299                               "utmi";
 300                 phys = <&u2phy0_host>;
 301                 phy-names = "usb";
 302                 power-domains = <&power RK3399_PD_PERIHP>;
 303                 status = "disabled";
 304         };
 305
 306         usb_host0_ohci: usb@fe3a0000 {
 307                 compatible = "generic-ohci";
 308                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 309                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 310                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 311                          <&u2phy0>;
 312                 clock-names = "usbhost", "arbiter",
 313                               "utmi";
 314                 phys = <&u2phy0_host>;
 315                 phy-names = "usb";
 316                 power-domains = <&power RK3399_PD_PERIHP>;
 317                 status = "disabled";
 318         };
 319
 320         usb_host1_ehci: usb@fe3c0000 {
 321                 compatible = "generic-ehci";
 322                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 323                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 324                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 325                          <&u2phy1>;
 326                 clock-names = "usbhost", "arbiter",
 327                               "utmi";
 328                 phys = <&u2phy1_host>;
 329                 phy-names = "usb";
 330                 power-domains = <&power RK3399_PD_PERIHP>;
 331                 status = "disabled";
 332         };
 333
 334         usb_host1_ohci: usb@fe3e0000 {
 335                 compatible = "generic-ohci";
 336                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 337                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 338                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 339                          <&u2phy1>;
 340                 clock-names = "usbhost", "arbiter",
 341                               "utmi";
 342                 phys = <&u2phy1_host>;
 343                 phy-names = "usb";
 344                 power-domains = <&power RK3399_PD_PERIHP>;
 345                 status = "disabled";
 346         };
 347
 348         usbdrd3_0: dwc3_typec0: usb@fe800000 {
 349                 compatible = "rockchip,rk3399-dwc3";
 350                 #address-cells = <2>;
 351                 #size-cells = <2>;
 352                 ranges;
 353                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 354                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 355                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 356                 clock-names = "ref_clk", "suspend_clk",
 357                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 358                               "aclk_usb3", "grf_clk";
 359                 resets = <&cru SRST_A_USB3_OTG0>;
 360                 reset-names = "usb3-otg";
 361                 status = "disabled";
 362
 363                 usbdrd_dwc3_0: dwc3 {
 364                         compatible = "snps,dwc3";
 365                         reg = <0x0 0xfe800000 0x0 0x100000>;
 366                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 367                         dr_mode = "otg";
 368                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 369                         phy-names = "usb2-phy", "usb3-phy";
 370                         phy_type = "utmi_wide";
 371                         snps,dis_enblslpm_quirk;
 372                         snps,dis-u2-freeclk-exists-quirk;
 373                         snps,dis_u2_susphy_quirk;
 374                         snps,dis-del-phy-power-chg-quirk;
 375                         snps,dis-tx-ipgap-linecheck-quirk;
 376                         power-domains = <&power RK3399_PD_USB3>;
 377                         status = "disabled";
 378                 };
 379         };
 380
 381         dwc3_typec1: usbdrd3_1: usb@fe900000 {
 382                 compatible = "rockchip,rk3399-dwc3";
 383                 #address-cells = <2>;
 384                 #size-cells = <2>;
 385                 ranges;
 386                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 387                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 388                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 389                 clock-names = "ref_clk", "suspend_clk",
 390                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 391                               "aclk_usb3", "grf_clk";
 392                 resets = <&cru SRST_A_USB3_OTG1>;
 393                 reset-names = "usb3-otg";
 394                 status = "disabled";
 395
 396                 usbdrd_dwc3_1: dwc3 {
 397                         compatible = "snps,dwc3";
 398                         reg = <0x0 0xfe900000 0x0 0x100000>;
 399                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 400                         dr_mode = "otg";
 401                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 402                         phy-names = "usb2-phy", "usb3-phy";
 403                         phy_type = "utmi_wide";
 404                         snps,dis_enblslpm_quirk;
 405                         snps,dis-u2-freeclk-exists-quirk;
 406                         snps,dis_u2_susphy_quirk;
 407                         snps,dis-del-phy-power-chg-quirk;
 408                         snps,dis-tx-ipgap-linecheck-quirk;
 409                         power-domains = <&power RK3399_PD_USB3>;
 410                         status = "disabled";
 411                 };
 412         };
 413
 414         cdn_dp: dp@fec00000 {
 415                 compatible = "rockchip,rk3399-cdn-dp";
 416                 reg = <0x0 0xfec00000 0x0 0x100000>;
 417                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 418                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 419                 assigned-clock-rates = <100000000>, <200000000>;
 420                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 421                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 422                 clock-names = "core-clk", "pclk", "spdif", "grf";
 423                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 424                 power-domains = <&power RK3399_PD_HDCP>;
 425                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 426                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 427                 reset-names = "spdif", "dptx", "apb", "core";
 428                 rockchip,grf = <&grf>;
 429                 #sound-dai-cells = <1>;
 430                 status = "disabled";
 431
 432                 ports {
 433                         dp_in: port {
 434                                 #address-cells = <1>;
 435                                 #size-cells = <0>;
 436
 437                                 dp_in_vopb: endpoint@0 {
 438                                         reg = <0>;
 439                                         remote-endpoint = <&vopb_out_dp>;
 440                                 };
 441
 442                                 dp_in_vopl: endpoint@1 {
 443                                         reg = <1>;
 444                                         remote-endpoint = <&vopl_out_dp>;
 445                                 };
 446                         };
 447                 };
 448         };
 449
 450         gic: interrupt-controller@fee00000 {
 451                 compatible = "arm,gic-v3";
 452                 #interrupt-cells = <4>;
 453                 #address-cells = <2>;
 454                 #size-cells = <2>;
 455                 ranges;
 456                 interrupt-controller;
 457
 458                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 459                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 460                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 461                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 462                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 463                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 464                 its: interrupt-controller@fee20000 {
 465                         compatible = "arm,gic-v3-its";
 466                         msi-controller;
 467                         reg = <0x0 0xfee20000 0x0 0x20000>;
 468                 };
 469
 470                 ppi-partitions {
 471                         ppi_cluster0: interrupt-partition-0 {
 472                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 473                         };
 474
 475                         ppi_cluster1: interrupt-partition-1 {
 476                                 affinity = <&cpu_b0 &cpu_b1>;
 477                         };
 478                 };
 479         };
 480
 481         saradc: saradc@ff100000 {
 482                 compatible = "rockchip,rk3399-saradc";
 483                 reg = <0x0 0xff100000 0x0 0x100>;
 484                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 485                 #io-channel-cells = <1>;
 486                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 487                 clock-names = "saradc", "apb_pclk";
 488                 resets = <&cru SRST_P_SARADC>;
 489                 reset-names = "saradc-apb";
 490                 status = "disabled";
 491         };
 492
 493         i2c1: i2c@ff110000 {
 494                 compatible = "rockchip,rk3399-i2c";
 495                 reg = <0x0 0xff110000 0x0 0x1000>;
 496                 assigned-clocks = <&cru SCLK_I2C1>;
 497                 assigned-clock-rates = <200000000>;
 498                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 499                 clock-names = "i2c", "pclk";
 500                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&i2c1_xfer>;
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 status = "disabled";
 506         };
 507
 508         i2c2: i2c@ff120000 {
 509                 compatible = "rockchip,rk3399-i2c";
 510                 reg = <0x0 0xff120000 0x0 0x1000>;
 511                 assigned-clocks = <&cru SCLK_I2C2>;
 512                 assigned-clock-rates = <200000000>;
 513                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 514                 clock-names = "i2c", "pclk";
 515                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&i2c2_xfer>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 status = "disabled";
 521         };
 522
 523         i2c3: i2c@ff130000 {
 524                 compatible = "rockchip,rk3399-i2c";
 525                 reg = <0x0 0xff130000 0x0 0x1000>;
 526                 assigned-clocks = <&cru SCLK_I2C3>;
 527                 assigned-clock-rates = <200000000>;
 528                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 529                 clock-names = "i2c", "pclk";
 530                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&i2c3_xfer>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         i2c5: i2c@ff140000 {
 539                 compatible = "rockchip,rk3399-i2c";
 540                 reg = <0x0 0xff140000 0x0 0x1000>;
 541                 assigned-clocks = <&cru SCLK_I2C5>;
 542                 assigned-clock-rates = <200000000>;
 543                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c5_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c6: i2c@ff150000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff150000 0x0 0x1000>;
 556                 assigned-clocks = <&cru SCLK_I2C6>;
 557                 assigned-clock-rates = <200000000>;
 558                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 559                 clock-names = "i2c", "pclk";
 560                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c6_xfer>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         i2c7: i2c@ff160000 {
 569                 compatible = "rockchip,rk3399-i2c";
 570                 reg = <0x0 0xff160000 0x0 0x1000>;
 571                 assigned-clocks = <&cru SCLK_I2C7>;
 572                 assigned-clock-rates = <200000000>;
 573                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 574                 clock-names = "i2c", "pclk";
 575                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c7_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         uart0: serial@ff180000 {
 584                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 585                 reg = <0x0 0xff180000 0x0 0x100>;
 586                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 587                 clock-names = "baudclk", "apb_pclk";
 588                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 589                 reg-shift = <2>;
 590                 reg-io-width = <4>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&uart0_xfer>;
 593                 status = "disabled";
 594         };
 595
 596         uart1: serial@ff190000 {
 597                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 598                 reg = <0x0 0xff190000 0x0 0x100>;
 599                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 600                 clock-names = "baudclk", "apb_pclk";
 601                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 602                 reg-shift = <2>;
 603                 reg-io-width = <4>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&uart1_xfer>;
 606                 status = "disabled";
 607         };
 608
 609         uart2: serial@ff1a0000 {
 610                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 611                 reg = <0x0 0xff1a0000 0x0 0x100>;
 612                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 613                 clock-names = "baudclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 615                 clock-frequency = <24000000>;
 616                 reg-shift = <2>;
 617                 reg-io-width = <4>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&uart2c_xfer>;
 620                 status = "disabled";
 621         };
 622
 623         uart3: serial@ff1b0000 {
 624                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 625                 reg = <0x0 0xff1b0000 0x0 0x100>;
 626                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 627                 clock-names = "baudclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 629                 reg-shift = <2>;
 630                 reg-io-width = <4>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&uart3_xfer>;
 633                 status = "disabled";
 634         };
 635
 636         spi0: spi@ff1c0000 {
 637                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 638                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 639                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 640                 clock-names = "spiclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         spi1: spi@ff1d0000 {
 650                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 651                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 652                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 653                 clock-names = "spiclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         spi2: spi@ff1e0000 {
 663                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 664                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 665                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 666                 clock-names = "spiclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 status = "disabled";
 673         };
 674
 675         spi4: spi@ff1f0000 {
 676                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 677                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 678                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 679                 clock-names = "spiclk", "apb_pclk";
 680                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 681                 pinctrl-names = "default";
 682                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 status = "disabled";
 686         };
 687
 688         spi5: spi@ff200000 {
 689                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 690                 reg = <0x0 0xff200000 0x0 0x1000>;
 691                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 692                 clock-names = "spiclk", "apb_pclk";
 693                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 696                 #address-cells = <1>;
 697                 #size-cells = <0>;
 698                 status = "disabled";
 699         };
 700
 701         thermal_zones: thermal-zones {
 702                 cpu_thermal: cpu {
 703                         polling-delay-passive = <100>;
 704                         polling-delay = <1000>;
 705
 706                         thermal-sensors = <&tsadc 0>;
 707
 708                         trips {
 709                                 cpu_alert0: cpu_alert0 {
 710                                         temperature = <70000>;
 711                                         hysteresis = <2000>;
 712                                         type = "passive";
 713                                 };
 714                                 cpu_alert1: cpu_alert1 {
 715                                         temperature = <75000>;
 716                                         hysteresis = <2000>;
 717                                         type = "passive";
 718                                 };
 719                                 cpu_crit: cpu_crit {
 720                                         temperature = <95000>;
 721                                         hysteresis = <2000>;
 722                                         type = "critical";
 723                                 };
 724                         };
 725
 726                         cooling-maps {
 727                                 map0 {
 728                                         trip = <&cpu_alert0>;
 729                                         cooling-device =
 730                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 731                                 };
 732                                 map1 {
 733                                         trip = <&cpu_alert1>;
 734                                         cooling-device =
 735                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 736                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 737                                 };
 738                         };
 739                 };
 740
 741                 gpu_thermal: gpu {
 742                         polling-delay-passive = <100>;
 743                         polling-delay = <1000>;
 744
 745                         thermal-sensors = <&tsadc 1>;
 746
 747                         trips {
 748                                 gpu_alert0: gpu_alert0 {
 749                                         temperature = <75000>;
 750                                         hysteresis = <2000>;
 751                                         type = "passive";
 752                                 };
 753                                 gpu_crit: gpu_crit {
 754                                         temperature = <95000>;
 755                                         hysteresis = <2000>;
 756                                         type = "critical";
 757                                 };
 758                         };
 759
 760                         cooling-maps {
 761                                 map0 {
 762                                         trip = <&gpu_alert0>;
 763                                         cooling-device =
 764                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 765                                 };
 766                         };
 767                 };
 768         };
 769
 770         tsadc: tsadc@ff260000 {
 771                 compatible = "rockchip,rk3399-tsadc";
 772                 reg = <0x0 0xff260000 0x0 0x100>;
 773                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 774                 assigned-clocks = <&cru SCLK_TSADC>;
 775                 assigned-clock-rates = <750000>;
 776                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 777                 clock-names = "tsadc", "apb_pclk";
 778                 resets = <&cru SRST_TSADC>;
 779                 reset-names = "tsadc-apb";
 780                 rockchip,grf = <&grf>;
 781                 rockchip,hw-tshut-temp = <95000>;
 782                 pinctrl-names = "init", "default", "sleep";
 783                 pinctrl-0 = <&otp_gpio>;
 784                 pinctrl-1 = <&otp_out>;
 785                 pinctrl-2 = <&otp_gpio>;
 786                 #thermal-sensor-cells = <1>;
 787                 status = "disabled";
 788         };
 789
 790         qos_emmc: qos@ffa58000 {
 791                 compatible = "syscon";
 792                 reg = <0x0 0xffa58000 0x0 0x20>;
 793         };
 794
 795         qos_gmac: qos@ffa5c000 {
 796                 compatible = "syscon";
 797                 reg = <0x0 0xffa5c000 0x0 0x20>;
 798         };
 799
 800         qos_pcie: qos@ffa60080 {
 801                 compatible = "syscon";
 802                 reg = <0x0 0xffa60080 0x0 0x20>;
 803         };
 804
 805         qos_usb_host0: qos@ffa60100 {
 806                 compatible = "syscon";
 807                 reg = <0x0 0xffa60100 0x0 0x20>;
 808         };
 809
 810         qos_usb_host1: qos@ffa60180 {
 811                 compatible = "syscon";
 812                 reg = <0x0 0xffa60180 0x0 0x20>;
 813         };
 814
 815         qos_usb_otg0: qos@ffa70000 {
 816                 compatible = "syscon";
 817                 reg = <0x0 0xffa70000 0x0 0x20>;
 818         };
 819
 820         qos_usb_otg1: qos@ffa70080 {
 821                 compatible = "syscon";
 822                 reg = <0x0 0xffa70080 0x0 0x20>;
 823         };
 824
 825         qos_sd: qos@ffa74000 {
 826                 compatible = "syscon";
 827                 reg = <0x0 0xffa74000 0x0 0x20>;
 828         };
 829
 830         qos_sdioaudio: qos@ffa76000 {
 831                 compatible = "syscon";
 832                 reg = <0x0 0xffa76000 0x0 0x20>;
 833         };
 834
 835         qos_hdcp: qos@ffa90000 {
 836                 compatible = "syscon";
 837                 reg = <0x0 0xffa90000 0x0 0x20>;
 838         };
 839
 840         qos_iep: qos@ffa98000 {
 841                 compatible = "syscon";
 842                 reg = <0x0 0xffa98000 0x0 0x20>;
 843         };
 844
 845         qos_isp0_m0: qos@ffaa0000 {
 846                 compatible = "syscon";
 847                 reg = <0x0 0xffaa0000 0x0 0x20>;
 848         };
 849
 850         qos_isp0_m1: qos@ffaa0080 {
 851                 compatible = "syscon";
 852                 reg = <0x0 0xffaa0080 0x0 0x20>;
 853         };
 854
 855         qos_isp1_m0: qos@ffaa8000 {
 856                 compatible = "syscon";
 857                 reg = <0x0 0xffaa8000 0x0 0x20>;
 858         };
 859
 860         qos_isp1_m1: qos@ffaa8080 {
 861                 compatible = "syscon";
 862                 reg = <0x0 0xffaa8080 0x0 0x20>;
 863         };
 864
 865         qos_rga_r: qos@ffab0000 {
 866                 compatible = "syscon";
 867                 reg = <0x0 0xffab0000 0x0 0x20>;
 868         };
 869
 870         qos_rga_w: qos@ffab0080 {
 871                 compatible = "syscon";
 872                 reg = <0x0 0xffab0080 0x0 0x20>;
 873         };
 874
 875         qos_video_m0: qos@ffab8000 {
 876                 compatible = "syscon";
 877                 reg = <0x0 0xffab8000 0x0 0x20>;
 878         };
 879
 880         qos_video_m1_r: qos@ffac0000 {
 881                 compatible = "syscon";
 882                 reg = <0x0 0xffac0000 0x0 0x20>;
 883         };
 884
 885         qos_video_m1_w: qos@ffac0080 {
 886                 compatible = "syscon";
 887                 reg = <0x0 0xffac0080 0x0 0x20>;
 888         };
 889
 890         qos_vop_big_r: qos@ffac8000 {
 891                 compatible = "syscon";
 892                 reg = <0x0 0xffac8000 0x0 0x20>;
 893         };
 894
 895         qos_vop_big_w: qos@ffac8080 {
 896                 compatible = "syscon";
 897                 reg = <0x0 0xffac8080 0x0 0x20>;
 898         };
 899
 900         qos_vop_little: qos@ffad0000 {
 901                 compatible = "syscon";
 902                 reg = <0x0 0xffad0000 0x0 0x20>;
 903         };
 904
 905         qos_perihp: qos@ffad8080 {
 906                 compatible = "syscon";
 907                 reg = <0x0 0xffad8080 0x0 0x20>;
 908         };
 909
 910         qos_gpu: qos@ffae0000 {
 911                 compatible = "syscon";
 912                 reg = <0x0 0xffae0000 0x0 0x20>;
 913         };
 914
 915         pmu: power-management@ff310000 {
 916                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 917                 reg = <0x0 0xff310000 0x0 0x1000>;
 918
 919                 /*
 920                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 921                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 922                  * Some of the power domains are grouped together for every
 923                  * voltage domain.
 924                  * The detail contents as below.
 925                  */
 926                 power: power-controller {
 927                         compatible = "rockchip,rk3399-power-controller";
 928                         #power-domain-cells = <1>;
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931
 932                         /* These power domains are grouped by VD_CENTER */
 933                         pd_iep@RK3399_PD_IEP {
 934                                 reg = <RK3399_PD_IEP>;
 935                                 clocks = <&cru ACLK_IEP>,
 936                                          <&cru HCLK_IEP>;
 937                                 pm_qos = <&qos_iep>;
 938                         };
 939                         pd_rga@RK3399_PD_RGA {
 940                                 reg = <RK3399_PD_RGA>;
 941                                 clocks = <&cru ACLK_RGA>,
 942                                          <&cru HCLK_RGA>;
 943                                 pm_qos = <&qos_rga_r>,
 944                                          <&qos_rga_w>;
 945                         };
 946                         pd_vcodec@RK3399_PD_VCODEC {
 947                                 reg = <RK3399_PD_VCODEC>;
 948                                 clocks = <&cru ACLK_VCODEC>,
 949                                          <&cru HCLK_VCODEC>;
 950                                 pm_qos = <&qos_video_m0>;
 951                         };
 952                         pd_vdu@RK3399_PD_VDU {
 953                                 reg = <RK3399_PD_VDU>;
 954                                 clocks = <&cru ACLK_VDU>,
 955                                          <&cru HCLK_VDU>;
 956                                 pm_qos = <&qos_video_m1_r>,
 957                                          <&qos_video_m1_w>;
 958                         };
 959
 960                         /* These power domains are grouped by VD_GPU */
 961                         pd_gpu@RK3399_PD_GPU {
 962                                 reg = <RK3399_PD_GPU>;
 963                                 clocks = <&cru ACLK_GPU>;
 964                                 pm_qos = <&qos_gpu>;
 965                         };
 966
 967                         /* These power domains are grouped by VD_LOGIC */
 968                         pd_edp@RK3399_PD_EDP {
 969                                 reg = <RK3399_PD_EDP>;
 970                                 clocks = <&cru PCLK_EDP_CTRL>;
 971                         };
 972                         pd_emmc@RK3399_PD_EMMC {
 973                                 reg = <RK3399_PD_EMMC>;
 974                                 clocks = <&cru ACLK_EMMC>;
 975                                 pm_qos = <&qos_emmc>;
 976                         };
 977                         pd_gmac@RK3399_PD_GMAC {
 978                                 reg = <RK3399_PD_GMAC>;
 979                                 clocks = <&cru ACLK_GMAC>,
 980                                          <&cru PCLK_GMAC>;
 981                                 pm_qos = <&qos_gmac>;
 982                         };
 983                         pd_perihp@RK3399_PD_PERIHP {
 984                                 reg = <RK3399_PD_PERIHP>;
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 clocks = <&cru ACLK_PERIHP>;
 988                                 pm_qos = <&qos_perihp>,
 989                                          <&qos_pcie>,
 990                                          <&qos_usb_host0>,
 991                                          <&qos_usb_host1>;
 992
 993                                 pd_sd@RK3399_PD_SD {
 994                                         reg = <RK3399_PD_SD>;
 995                                         clocks = <&cru HCLK_SDMMC>,
 996                                                  <&cru SCLK_SDMMC>;
 997                                         pm_qos = <&qos_sd>;
 998                                 };
 999                         };
1000                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1001                                 reg = <RK3399_PD_SDIOAUDIO>;
1002                                 clocks = <&cru HCLK_SDIO>;
1003                                 pm_qos = <&qos_sdioaudio>;
1004                         };
1005                         pd_usb3@RK3399_PD_USB3 {
1006                                 reg = <RK3399_PD_USB3>;
1007                                 clocks = <&cru ACLK_USB3>;
1008                                 pm_qos = <&qos_usb_otg0>,
1009                                          <&qos_usb_otg1>;
1010                         };
1011                         pd_vio@RK3399_PD_VIO {
1012                                 reg = <RK3399_PD_VIO>;
1013                                 #address-cells = <1>;
1014                                 #size-cells = <0>;
1015
1016                                 pd_hdcp@RK3399_PD_HDCP {
1017                                         reg = <RK3399_PD_HDCP>;
1018                                         clocks = <&cru ACLK_HDCP>,
1019                                                  <&cru HCLK_HDCP>,
1020                                                  <&cru PCLK_HDCP>;
1021                                         pm_qos = <&qos_hdcp>;
1022                                 };
1023                                 pd_isp0@RK3399_PD_ISP0 {
1024                                         reg = <RK3399_PD_ISP0>;
1025                                         clocks = <&cru ACLK_ISP0>,
1026                                                  <&cru HCLK_ISP0>;
1027                                         pm_qos = <&qos_isp0_m0>,
1028                                                  <&qos_isp0_m1>;
1029                                 };
1030                                 pd_isp1@RK3399_PD_ISP1 {
1031                                         reg = <RK3399_PD_ISP1>;
1032                                         clocks = <&cru ACLK_ISP1>,
1033                                                  <&cru HCLK_ISP1>;
1034                                         pm_qos = <&qos_isp1_m0>,
1035                                                  <&qos_isp1_m1>;
1036                                 };
1037                                 pd_tcpc0@RK3399_PD_TCPC0 {
1038                                         reg = <RK3399_PD_TCPD0>;
1039                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1040                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1041                                 };
1042                                 pd_tcpc1@RK3399_PD_TCPC1 {
1043                                         reg = <RK3399_PD_TCPD1>;
1044                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1045                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1046                                 };
1047                                 pd_vo@RK3399_PD_VO {
1048                                         reg = <RK3399_PD_VO>;
1049                                         #address-cells = <1>;
1050                                         #size-cells = <0>;
1051
1052                                         pd_vopb@RK3399_PD_VOPB {
1053                                                 reg = <RK3399_PD_VOPB>;
1054                                                 clocks = <&cru ACLK_VOP0>,
1055                                                          <&cru HCLK_VOP0>;
1056                                                 pm_qos = <&qos_vop_big_r>,
1057                                                          <&qos_vop_big_w>;
1058                                         };
1059                                         pd_vopl@RK3399_PD_VOPL {
1060                                                 reg = <RK3399_PD_VOPL>;
1061                                                 clocks = <&cru ACLK_VOP1>,
1062                                                          <&cru HCLK_VOP1>;
1063                                                 pm_qos = <&qos_vop_little>;
1064                                         };
1065                                 };
1066                         };
1067                 };
1068         };
1069
1070         pmugrf: syscon@ff320000 {
1071                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1072                 reg = <0x0 0xff320000 0x0 0x1000>;
1073
1074                 pmu_io_domains: io-domains {
1075                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1076                         status = "disabled";
1077                 };
1078         };
1079
1080         spi3: spi@ff350000 {
1081                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1082                 reg = <0x0 0xff350000 0x0 0x1000>;
1083                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1084                 clock-names = "spiclk", "apb_pclk";
1085                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1086                 pinctrl-names = "default";
1087                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1088                 #address-cells = <1>;
1089                 #size-cells = <0>;
1090                 status = "disabled";
1091         };
1092
1093         uart4: serial@ff370000 {
1094                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1095                 reg = <0x0 0xff370000 0x0 0x100>;
1096                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1097                 clock-names = "baudclk", "apb_pclk";
1098                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1099                 reg-shift = <2>;
1100                 reg-io-width = <4>;
1101                 pinctrl-names = "default";
1102                 pinctrl-0 = <&uart4_xfer>;
1103                 status = "disabled";
1104         };
1105
1106         i2c0: i2c@ff3c0000 {
1107                 compatible = "rockchip,rk3399-i2c";
1108                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1109                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1110                 assigned-clock-rates = <200000000>;
1111                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1112                 clock-names = "i2c", "pclk";
1113                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1114                 pinctrl-names = "default";
1115                 pinctrl-0 = <&i2c0_xfer>;
1116                 #address-cells = <1>;
1117                 #size-cells = <0>;
1118                 status = "disabled";
1119         };
1120
1121         i2c4: i2c@ff3d0000 {
1122                 compatible = "rockchip,rk3399-i2c";
1123                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1124                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1125                 assigned-clock-rates = <200000000>;
1126                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1127                 clock-names = "i2c", "pclk";
1128                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1129                 pinctrl-names = "default";
1130                 pinctrl-0 = <&i2c4_xfer>;
1131                 #address-cells = <1>;
1132                 #size-cells = <0>;
1133                 status = "disabled";
1134         };
1135
1136         i2c8: i2c@ff3e0000 {
1137                 compatible = "rockchip,rk3399-i2c";
1138                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1139                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1140                 assigned-clock-rates = <200000000>;
1141                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1142                 clock-names = "i2c", "pclk";
1143                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1144                 pinctrl-names = "default";
1145                 pinctrl-0 = <&i2c8_xfer>;
1146                 #address-cells = <1>;
1147                 #size-cells = <0>;
1148                 status = "disabled";
1149         };
1150
1151         pwm0: pwm@ff420000 {
1152                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1153                 reg = <0x0 0xff420000 0x0 0x10>;
1154                 #pwm-cells = <3>;
1155                 pinctrl-names = "default";
1156                 pinctrl-0 = <&pwm0_pin>;
1157                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1158                 clock-names = "pwm";
1159                 status = "disabled";
1160         };
1161
1162         pwm1: pwm@ff420010 {
1163                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1164                 reg = <0x0 0xff420010 0x0 0x10>;
1165                 #pwm-cells = <3>;
1166                 pinctrl-names = "default";
1167                 pinctrl-0 = <&pwm1_pin>;
1168                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1169                 clock-names = "pwm";
1170                 status = "disabled";
1171         };
1172
1173         pwm2: pwm@ff420020 {
1174                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1175                 reg = <0x0 0xff420020 0x0 0x10>;
1176                 #pwm-cells = <3>;
1177                 pinctrl-names = "default";
1178                 pinctrl-0 = <&pwm2_pin>;
1179                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1180                 clock-names = "pwm";
1181                 status = "disabled";
1182         };
1183
1184         pwm3: pwm@ff420030 {
1185                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1186                 reg = <0x0 0xff420030 0x0 0x10>;
1187                 #pwm-cells = <3>;
1188                 pinctrl-names = "default";
1189                 pinctrl-0 = <&pwm3a_pin>;
1190                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1191                 clock-names = "pwm";
1192                 status = "disabled";
1193         };
1194
1195         efuse0: efuse@ff690000 {
1196                 compatible = "rockchip,rk3399-efuse";
1197                 reg = <0x0 0xff690000 0x0 0x80>;
1198                 #address-cells = <1>;
1199                 #size-cells = <1>;
1200                 clocks = <&cru PCLK_EFUSE1024NS>;
1201                 clock-names = "pclk_efuse";
1202
1203                 /* Data cells */
1204                 cpu_id: cpu-id@7 {
1205                         reg = <0x07 0x10>;
1206                 };
1207                 cpub_leakage: cpu-leakage@17 {
1208                         reg = <0x17 0x1>;
1209                 };
1210                 gpu_leakage: gpu-leakage@18 {
1211                         reg = <0x18 0x1>;
1212                 };
1213                 center_leakage: center-leakage@19 {
1214                         reg = <0x19 0x1>;
1215                 };
1216                 cpul_leakage: cpu-leakage@1a {
1217                         reg = <0x1a 0x1>;
1218                 };
1219                 logic_leakage: logic-leakage@1b {
1220                         reg = <0x1b 0x1>;
1221                 };
1222                 wafer_info: wafer-info@1c {
1223                         reg = <0x1c 0x1>;
1224                 };
1225         };
1226
1227         pmucru: pmu-clock-controller@ff750000 {
1228                 compatible = "rockchip,rk3399-pmucru";
1229                 reg = <0x0 0xff750000 0x0 0x1000>;
1230                 rockchip,grf = <&pmugrf>;
1231                 #clock-cells = <1>;
1232                 #reset-cells = <1>;
1233                 assigned-clocks = <&pmucru PLL_PPLL>;
1234                 assigned-clock-rates = <676000000>;
1235         };
1236
1237         cru: clock-controller@ff760000 {
1238                 compatible = "rockchip,rk3399-cru";
1239                 reg = <0x0 0xff760000 0x0 0x1000>;
1240                 rockchip,grf = <&grf>;
1241                 #clock-cells = <1>;
1242                 #reset-cells = <1>;
1243                 assigned-clocks =
1244                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1245                         <&cru PLL_NPLL>,
1246                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1247                         <&cru PCLK_PERIHP>,
1248                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1249                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1250                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1251                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1252                         <&cru ACLK_GIC_PRE>,
1253                         <&cru PCLK_DDR>;
1254                 assigned-clock-rates =
1255                          <594000000>,  <800000000>,
1256                         <1000000000>,
1257                          <150000000>,   <75000000>,
1258                           <37500000>,
1259                          <100000000>,  <100000000>,
1260                           <50000000>, <600000000>,
1261                          <100000000>,   <50000000>,
1262                          <400000000>, <400000000>,
1263                          <200000000>,
1264                          <200000000>;
1265         };
1266
1267         grf: syscon@ff770000 {
1268                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1269                 reg = <0x0 0xff770000 0x0 0x10000>;
1270                 #address-cells = <1>;
1271                 #size-cells = <1>;
1272
1273                 io_domains: io-domains {
1274                         compatible = "rockchip,rk3399-io-voltage-domain";
1275                         status = "disabled";
1276                 };
1277
1278                 u2phy0: usb2-phy@e450 {
1279                         compatible = "rockchip,rk3399-usb2phy";
1280                         reg = <0xe450 0x10>;
1281                         clocks = <&cru SCLK_USB2PHY0_REF>;
1282                         clock-names = "phyclk";
1283                         #clock-cells = <0>;
1284                         clock-output-names = "clk_usbphy0_480m";
1285                         status = "disabled";
1286
1287                         u2phy0_host: host-port {
1288                                 #phy-cells = <0>;
1289                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1290                                 interrupt-names = "linestate";
1291                                 status = "disabled";
1292                         };
1293
1294                         u2phy0_otg: otg-port {
1295                                 #phy-cells = <0>;
1296                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1297                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1298                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1299                                 interrupt-names = "otg-bvalid", "otg-id",
1300                                                   "linestate";
1301                                 status = "disabled";
1302                         };
1303                 };
1304
1305                 u2phy1: usb2-phy@e460 {
1306                         compatible = "rockchip,rk3399-usb2phy";
1307                         reg = <0xe460 0x10>;
1308                         clocks = <&cru SCLK_USB2PHY1_REF>;
1309                         clock-names = "phyclk";
1310                         #clock-cells = <0>;
1311                         clock-output-names = "clk_usbphy1_480m";
1312                         status = "disabled";
1313
1314                         u2phy1_host: host-port {
1315                                 #phy-cells = <0>;
1316                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1317                                 interrupt-names = "linestate";
1318                                 status = "disabled";
1319                         };
1320
1321                         u2phy1_otg: otg-port {
1322                                 #phy-cells = <0>;
1323                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1324                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1325                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1326                                 interrupt-names = "otg-bvalid", "otg-id",
1327                                                   "linestate";
1328                                 status = "disabled";
1329                         };
1330                 };
1331
1332                 emmc_phy: phy@f780 {
1333                         compatible = "rockchip,rk3399-emmc-phy";
1334                         reg = <0xf780 0x24>;
1335                         clocks = <&sdhci>;
1336                         clock-names = "emmcclk";
1337                         #phy-cells = <0>;
1338                         status = "disabled";
1339                 };
1340
1341                 pcie_phy: pcie-phy {
1342                         compatible = "rockchip,rk3399-pcie-phy";
1343                         clocks = <&cru SCLK_PCIEPHY_REF>;
1344                         clock-names = "refclk";
1345                         #phy-cells = <0>;
1346                         resets = <&cru SRST_PCIEPHY>;
1347                         reset-names = "phy";
1348                         status = "disabled";
1349                 };
1350         };
1351
1352         tcphy0: phy@ff7c0000 {
1353                 compatible = "rockchip,rk3399-typec-phy";
1354                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1355                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1356                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1357                 clock-names = "tcpdcore", "tcpdphy-ref";
1358                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1359                 assigned-clock-rates = <50000000>;
1360                 power-domains = <&power RK3399_PD_TCPD0>;
1361                 resets = <&cru SRST_UPHY0>,
1362                          <&cru SRST_UPHY0_PIPE_L00>,
1363                          <&cru SRST_P_UPHY0_TCPHY>;
1364                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1365                 rockchip,grf = <&grf>;
1366                 status = "disabled";
1367
1368                 tcphy0_dp: dp-port {
1369                         #phy-cells = <0>;
1370                 };
1371
1372                 tcphy0_usb3: usb3-port {
1373                         #phy-cells = <0>;
1374                 };
1375         };
1376
1377         tcphy1: phy@ff800000 {
1378                 compatible = "rockchip,rk3399-typec-phy";
1379                 reg = <0x0 0xff800000 0x0 0x40000>;
1380                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1381                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1382                 clock-names = "tcpdcore", "tcpdphy-ref";
1383                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1384                 assigned-clock-rates = <50000000>;
1385                 power-domains = <&power RK3399_PD_TCPD1>;
1386                 resets = <&cru SRST_UPHY1>,
1387                          <&cru SRST_UPHY1_PIPE_L00>,
1388                          <&cru SRST_P_UPHY1_TCPHY>;
1389                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1390                 rockchip,grf = <&grf>;
1391                 status = "disabled";
1392
1393                 tcphy1_dp: dp-port {
1394                         #phy-cells = <0>;
1395                 };
1396
1397                 tcphy1_usb3: usb3-port {
1398                         #phy-cells = <0>;
1399                 };
1400         };
1401
1402         watchdog@ff848000 {
1403                 compatible = "snps,dw-wdt";
1404                 reg = <0x0 0xff848000 0x0 0x100>;
1405                 clocks = <&cru PCLK_WDT>;
1406                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1407         };
1408
1409         rktimer: rktimer@ff850000 {
1410                 compatible = "rockchip,rk3399-timer";
1411                 reg = <0x0 0xff850000 0x0 0x1000>;
1412                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1413                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1414                 clock-names = "pclk", "timer";
1415         };
1416
1417         spdif: spdif@ff870000 {
1418                 compatible = "rockchip,rk3399-spdif";
1419                 reg = <0x0 0xff870000 0x0 0x1000>;
1420                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1421                 dmas = <&dmac_bus 7>;
1422                 dma-names = "tx";
1423                 clock-names = "mclk", "hclk";
1424                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1425                 pinctrl-names = "default";
1426                 pinctrl-0 = <&spdif_bus>;
1427                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1428                 #sound-dai-cells = <0>;
1429                 status = "disabled";
1430         };
1431
1432         i2s0: i2s@ff880000 {
1433                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1434                 reg = <0x0 0xff880000 0x0 0x1000>;
1435                 rockchip,grf = <&grf>;
1436                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1437                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1438                 dma-names = "tx", "rx";
1439                 clock-names = "i2s_clk", "i2s_hclk";
1440                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1441                 pinctrl-names = "default";
1442                 pinctrl-0 = <&i2s0_8ch_bus>;
1443                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1444                 #sound-dai-cells = <0>;
1445                 status = "disabled";
1446         };
1447
1448         i2s1: i2s@ff890000 {
1449                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1450                 reg = <0x0 0xff890000 0x0 0x1000>;
1451                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1452                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1453                 dma-names = "tx", "rx";
1454                 clock-names = "i2s_clk", "i2s_hclk";
1455                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1456                 pinctrl-names = "default";
1457                 pinctrl-0 = <&i2s1_2ch_bus>;
1458                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1459                 #sound-dai-cells = <0>;
1460                 status = "disabled";
1461         };
1462
1463         i2s2: i2s@ff8a0000 {
1464                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1465                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1466                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1467                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1468                 dma-names = "tx", "rx";
1469                 clock-names = "i2s_clk", "i2s_hclk";
1470                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1471                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1472                 #sound-dai-cells = <0>;
1473                 status = "disabled";
1474         };
1475
1476         vopl: vop@ff8f0000 {
1477                 compatible = "rockchip,rk3399-vop-lit";
1478                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1479                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1480                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1481                 assigned-clock-rates = <400000000>, <100000000>;
1482                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1483                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1484                 iommus = <&vopl_mmu>;
1485                 power-domains = <&power RK3399_PD_VOPL>;
1486                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1487                 reset-names = "axi", "ahb", "dclk";
1488                 status = "disabled";
1489
1490                 vopl_out: port {
1491                         #address-cells = <1>;
1492                         #size-cells = <0>;
1493
1494                         vopl_out_mipi: endpoint@0 {
1495                                 reg = <0>;
1496                                 remote-endpoint = <&mipi_in_vopl>;
1497                         };
1498
1499                         vopl_out_edp: endpoint@1 {
1500                                 reg = <1>;
1501                                 remote-endpoint = <&edp_in_vopl>;
1502                         };
1503
1504                         vopl_out_hdmi: endpoint@2 {
1505                                 reg = <2>;
1506                                 remote-endpoint = <&hdmi_in_vopl>;
1507                         };
1508
1509                         vopl_out_mipi1: endpoint@3 {
1510                                 reg = <3>;
1511                                 remote-endpoint = <&mipi1_in_vopl>;
1512                         };
1513
1514                         vopl_out_dp: endpoint@4 {
1515                                 reg = <4>;
1516                                 remote-endpoint = <&dp_in_vopl>;
1517                         };
1518                 };
1519         };
1520
1521         vopl_mmu: iommu@ff8f3f00 {
1522                 compatible = "rockchip,iommu";
1523                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1524                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1525                 interrupt-names = "vopl_mmu";
1526                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1527                 clock-names = "aclk", "iface";
1528                 power-domains = <&power RK3399_PD_VOPL>;
1529                 #iommu-cells = <0>;
1530                 status = "disabled";
1531         };
1532
1533         vopb: vop@ff900000 {
1534                 compatible = "rockchip,rk3399-vop-big";
1535                 reg = <0x0 0xff900000 0x0 0x3efc>;
1536                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1537                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1538                 assigned-clock-rates = <400000000>, <100000000>;
1539                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1540                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1541                 iommus = <&vopb_mmu>;
1542                 power-domains = <&power RK3399_PD_VOPB>;
1543                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1544                 reset-names = "axi", "ahb", "dclk";
1545                 status = "disabled";
1546
1547                 vopb_out: port {
1548                         #address-cells = <1>;
1549                         #size-cells = <0>;
1550
1551                         vopb_out_edp: endpoint@0 {
1552                                 reg = <0>;
1553                                 remote-endpoint = <&edp_in_vopb>;
1554                         };
1555
1556                         vopb_out_mipi: endpoint@1 {
1557                                 reg = <1>;
1558                                 remote-endpoint = <&mipi_in_vopb>;
1559                         };
1560
1561                         vopb_out_hdmi: endpoint@2 {
1562                                 reg = <2>;
1563                                 remote-endpoint = <&hdmi_in_vopb>;
1564                         };
1565
1566                         vopb_out_mipi1: endpoint@3 {
1567                                 reg = <3>;
1568                                 remote-endpoint = <&mipi1_in_vopb>;
1569                         };
1570
1571                         vopb_out_dp: endpoint@4 {
1572                                 reg = <4>;
1573                                 remote-endpoint = <&dp_in_vopb>;
1574                         };
1575                 };
1576         };
1577
1578         vopb_mmu: iommu@ff903f00 {
1579                 compatible = "rockchip,iommu";
1580                 reg = <0x0 0xff903f00 0x0 0x100>;
1581                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1582                 interrupt-names = "vopb_mmu";
1583                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1584                 clock-names = "aclk", "iface";
1585                 power-domains = <&power RK3399_PD_VOPB>;
1586                 #iommu-cells = <0>;
1587                 status = "disabled";
1588         };
1589
1590         isp0_mmu: iommu@ff914000 {
1591                 compatible = "rockchip,iommu";
1592                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1593                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1594                 interrupt-names = "isp0_mmu";
1595                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1596                 clock-names = "aclk", "iface";
1597                 #iommu-cells = <0>;
1598                 rockchip,disable-mmu-reset;
1599                 status = "disabled";
1600         };
1601
1602         isp1_mmu: iommu@ff924000 {
1603                 compatible = "rockchip,iommu";
1604                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1605                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1606                 interrupt-names = "isp1_mmu";
1607                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1608                 clock-names = "aclk", "iface";
1609                 #iommu-cells = <0>;
1610                 rockchip,disable-mmu-reset;
1611                 status = "disabled";
1612         };
1613
1614         hdmi_sound: hdmi-sound {
1615                 compatible = "simple-audio-card";
1616                 simple-audio-card,format = "i2s";
1617                 simple-audio-card,mclk-fs = <256>;
1618                 simple-audio-card,name = "hdmi-sound";
1619                 status = "disabled";
1620
1621                 simple-audio-card,cpu {
1622                         sound-dai = <&i2s2>;
1623                 };
1624                 simple-audio-card,codec {
1625                         sound-dai = <&hdmi>;
1626                 };
1627         };
1628
1629         hdmi: hdmi@ff940000 {
1630                 compatible = "rockchip,rk3399-dw-hdmi";
1631                 reg = <0x0 0xff940000 0x0 0x20000>;
1632                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1633                 clocks = <&cru PCLK_HDMI_CTRL>,
1634                          <&cru SCLK_HDMI_SFR>,
1635                          <&cru PLL_VPLL>,
1636                          <&cru PCLK_VIO_GRF>,
1637                          <&cru SCLK_HDMI_CEC>;
1638                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1639                 power-domains = <&power RK3399_PD_HDCP>;
1640                 reg-io-width = <4>;
1641                 rockchip,grf = <&grf>;
1642                 #sound-dai-cells = <0>;
1643                 status = "disabled";
1644
1645                 ports {
1646                         hdmi_in: port {
1647                                 #address-cells = <1>;
1648                                 #size-cells = <0>;
1649
1650                                 hdmi_in_vopb: endpoint@0 {
1651                                         reg = <0>;
1652                                         remote-endpoint = <&vopb_out_hdmi>;
1653                                 };
1654                                 hdmi_in_vopl: endpoint@1 {
1655                                         reg = <1>;
1656                                         remote-endpoint = <&vopl_out_hdmi>;
1657                                 };
1658                         };
1659                 };
1660         };
1661
1662         mipi_dsi: mipi@ff960000 {
1663                 compatible = "rockchip,rk3399_mipi_dsi";
1664                 reg = <0x0 0xff960000 0x0 0x8000>;
1665                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1666                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1667                          <&cru SCLK_DPHY_TX0_CFG>;
1668                 clock-names = "ref", "pclk", "phy_cfg";
1669                 rockchip,grf = <&grf>;
1670                 #address-cells = <1>;
1671                 #size-cells = <0>;
1672                 status = "disabled";
1673                 ports {
1674                         reg = <1>;
1675                         mipi_in: port {
1676                                 #address-cells = <1>;
1677                                 #size-cells = <0>;
1678                                 mipi_in_vopb: endpoint@0 {
1679                                         reg = <0>;
1680                                         remote-endpoint = <&vopb_out_mipi>;
1681                                 };
1682                                 mipi_in_vopl: endpoint@1 {
1683                                         reg = <1>;
1684                                         remote-endpoint = <&vopl_out_mipi>;
1685                                 };
1686                         };
1687                 };
1688         };
1689
1690         mipi_dsi1: mipi@ff968000 {
1691                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1692                 reg = <0x0 0xff968000 0x0 0x8000>;
1693                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1694                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1695                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1696                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1697                 power-domains = <&power RK3399_PD_VIO>;
1698                 resets = <&cru SRST_P_MIPI_DSI1>;
1699                 reset-names = "apb";
1700                 rockchip,grf = <&grf>;
1701                 status = "disabled";
1702
1703                 ports {
1704                         #address-cells = <1>;
1705                         #size-cells = <0>;
1706
1707                         mipi1_in: port@0 {
1708                                 reg = <0>;
1709                                 #address-cells = <1>;
1710                                 #size-cells = <0>;
1711
1712                                 mipi1_in_vopb: endpoint@0 {
1713                                         reg = <0>;
1714                                         remote-endpoint = <&vopb_out_mipi1>;
1715                                 };
1716
1717                                 mipi1_in_vopl: endpoint@1 {
1718                                         reg = <1>;
1719                                         remote-endpoint = <&vopl_out_mipi1>;
1720                                 };
1721                         };
1722                 };
1723         };
1724
1725         edp: edp@ff970000 {
1726                 compatible = "rockchip,rk3399-edp";
1727                 reg = <0x0 0xff970000 0x0 0x8000>;
1728                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1729                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1730                 clock-names = "dp", "pclk", "grf";
1731                 pinctrl-names = "default";
1732                 pinctrl-0 = <&edp_hpd>;
1733                 power-domains = <&power RK3399_PD_EDP>;
1734                 resets = <&cru SRST_P_EDP_CTRL>;
1735                 reset-names = "dp";
1736                 rockchip,grf = <&grf>;
1737                 status = "disabled";
1738
1739                 ports {
1740                         #address-cells = <1>;
1741                         #size-cells = <0>;
1742                         edp_in: port@0 {
1743                                 reg = <0>;
1744                                 #address-cells = <1>;
1745                                 #size-cells = <0>;
1746
1747                                 edp_in_vopb: endpoint@0 {
1748                                         reg = <0>;
1749                                         remote-endpoint = <&vopb_out_edp>;
1750                                 };
1751
1752                                 edp_in_vopl: endpoint@1 {
1753                                         reg = <1>;
1754                                         remote-endpoint = <&vopl_out_edp>;
1755                                 };
1756                         };
1757                 };
1758         };
1759
1760         gpu: gpu@ff9a0000 {
1761                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1762                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1763                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1764                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1765                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1766                 interrupt-names = "gpu", "job", "mmu";
1767                 clocks = <&cru ACLK_GPU>;
1768                 power-domains = <&power RK3399_PD_GPU>;
1769                 status = "disabled";
1770         };
1771
1772         pinctrl: pinctrl {
1773                 compatible = "rockchip,rk3399-pinctrl";
1774                 rockchip,grf = <&grf>;
1775                 rockchip,pmu = <&pmugrf>;
1776                 #address-cells = <2>;
1777                 #size-cells = <2>;
1778                 ranges;
1779
1780                 gpio0: gpio0@ff720000 {
1781                         compatible = "rockchip,gpio-bank";
1782                         reg = <0x0 0xff720000 0x0 0x100>;
1783                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1784                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1785
1786                         gpio-controller;
1787                         #gpio-cells = <0x2>;
1788
1789                         interrupt-controller;
1790                         #interrupt-cells = <0x2>;
1791                 };
1792
1793                 gpio1: gpio1@ff730000 {
1794                         compatible = "rockchip,gpio-bank";
1795                         reg = <0x0 0xff730000 0x0 0x100>;
1796                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1797                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1798
1799                         gpio-controller;
1800                         #gpio-cells = <0x2>;
1801
1802                         interrupt-controller;
1803                         #interrupt-cells = <0x2>;
1804                 };
1805
1806                 gpio2: gpio2@ff780000 {
1807                         compatible = "rockchip,gpio-bank";
1808                         reg = <0x0 0xff780000 0x0 0x100>;
1809                         clocks = <&cru PCLK_GPIO2>;
1810                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1811
1812                         gpio-controller;
1813                         #gpio-cells = <0x2>;
1814
1815                         interrupt-controller;
1816                         #interrupt-cells = <0x2>;
1817                 };
1818
1819                 gpio3: gpio3@ff788000 {
1820                         compatible = "rockchip,gpio-bank";
1821                         reg = <0x0 0xff788000 0x0 0x100>;
1822                         clocks = <&cru PCLK_GPIO3>;
1823                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1824
1825                         gpio-controller;
1826                         #gpio-cells = <0x2>;
1827
1828                         interrupt-controller;
1829                         #interrupt-cells = <0x2>;
1830                 };
1831
1832                 gpio4: gpio4@ff790000 {
1833                         compatible = "rockchip,gpio-bank";
1834                         reg = <0x0 0xff790000 0x0 0x100>;
1835                         clocks = <&cru PCLK_GPIO4>;
1836                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1837
1838                         gpio-controller;
1839                         #gpio-cells = <0x2>;
1840
1841                         interrupt-controller;
1842                         #interrupt-cells = <0x2>;
1843                 };
1844
1845                 pcfg_pull_up: pcfg-pull-up {
1846                         bias-pull-up;
1847                 };
1848
1849                 pcfg_pull_down: pcfg-pull-down {
1850                         bias-pull-down;
1851                 };
1852
1853                 pcfg_pull_none: pcfg-pull-none {
1854                         bias-disable;
1855                 };
1856
1857                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1858                         bias-disable;
1859                         drive-strength = <12>;
1860                 };
1861
1862                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1863                         bias-disable;
1864                         drive-strength = <13>;
1865                 };
1866
1867                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1868                         bias-disable;
1869                         drive-strength = <18>;
1870                 };
1871
1872                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1873                         bias-disable;
1874                         drive-strength = <20>;
1875                 };
1876
1877                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1878                         bias-pull-up;
1879                         drive-strength = <2>;
1880                 };
1881
1882                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1883                         bias-pull-up;
1884                         drive-strength = <8>;
1885                 };
1886
1887                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1888                         bias-pull-up;
1889                         drive-strength = <18>;
1890                 };
1891
1892                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1893                         bias-pull-up;
1894                         drive-strength = <20>;
1895                 };
1896
1897                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1898                         bias-pull-down;
1899                         drive-strength = <4>;
1900                 };
1901
1902                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
1903                         bias-pull-down;
1904                         drive-strength = <8>;
1905                 };
1906
1907                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1908                         bias-pull-down;
1909                         drive-strength = <12>;
1910                 };
1911
1912                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
1913                         bias-pull-down;
1914                         drive-strength = <18>;
1915                 };
1916
1917                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
1918                         bias-pull-down;
1919                         drive-strength = <20>;
1920                 };
1921
1922                 pcfg_output_high: pcfg-output-high {
1923                         output-high;
1924                 };
1925
1926                 pcfg_output_low: pcfg-output-low {
1927                         output-low;
1928                 };
1929
1930                 clock {
1931                         clk_32k: clk-32k {
1932                                 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
1933                         };
1934                 };
1935
1936                 edp {
1937                         edp_hpd: edp-hpd {
1938                                 rockchip,pins =
1939                                         <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1940                         };
1941                 };
1942
1943                 gmac {
1944                         rgmii_pins: rgmii-pins {
1945                                 rockchip,pins =
1946                                         /* mac_txclk */
1947                                         <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1948                                         /* mac_rxclk */
1949                                         <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
1950                                         /* mac_mdio */
1951                                         <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1952                                         /* mac_txen */
1953                                         <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1954                                         /* mac_clk */
1955                                         <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1956                                         /* mac_rxdv */
1957                                         <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
1958                                         /* mac_mdc */
1959                                         <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1960                                         /* mac_rxd1 */
1961                                         <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
1962                                         /* mac_rxd0 */
1963                                         <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1964                                         /* mac_txd1 */
1965                                         <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1966                                         /* mac_txd0 */
1967                                         <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1968                                         /* mac_rxd3 */
1969                                         <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
1970                                         /* mac_rxd2 */
1971                                         <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
1972                                         /* mac_txd3 */
1973                                         <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1974                                         /* mac_txd2 */
1975                                         <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1976                         };
1977
1978                         rmii_pins: rmii-pins {
1979                                 rockchip,pins =
1980                                         /* mac_mdio */
1981                                         <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1982                                         /* mac_txen */
1983                                         <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1984                                         /* mac_clk */
1985                                         <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1986                                         /* mac_rxer */
1987                                         <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
1988                                         /* mac_rxdv */
1989                                         <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
1990                                         /* mac_mdc */
1991                                         <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1992                                         /* mac_rxd1 */
1993                                         <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
1994                                         /* mac_rxd0 */
1995                                         <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1996                                         /* mac_txd1 */
1997                                         <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1998                                         /* mac_txd0 */
1999                                         <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2000                         };
2001                 };
2002
2003                 i2c0 {
2004                         i2c0_xfer: i2c0-xfer {
2005                                 rockchip,pins =
2006                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
2007                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
2008                         };
2009                 };
2010
2011                 i2c1 {
2012                         i2c1_xfer: i2c1-xfer {
2013                                 rockchip,pins =
2014                                         <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
2015                                         <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
2016                         };
2017                 };
2018
2019                 i2c2 {
2020                         i2c2_xfer: i2c2-xfer {
2021                                 rockchip,pins =
2022                                         <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2023                                         <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2024                         };
2025                 };
2026
2027                 i2c3 {
2028                         i2c3_xfer: i2c3-xfer {
2029                                 rockchip,pins =
2030                                         <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
2031                                         <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
2032                         };
2033                 };
2034
2035                 i2c4 {
2036                         i2c4_xfer: i2c4-xfer {
2037                                 rockchip,pins =
2038                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
2039                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
2040                         };
2041                 };
2042
2043                 i2c5 {
2044                         i2c5_xfer: i2c5-xfer {
2045                                 rockchip,pins =
2046                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
2047                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>;
2048                         };
2049                 };
2050
2051                 i2c6 {
2052                         i2c6_xfer: i2c6-xfer {
2053                                 rockchip,pins =
2054                                         <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
2055                                         <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
2056                         };
2057                 };
2058
2059                 i2c7 {
2060                         i2c7_xfer: i2c7-xfer {
2061                                 rockchip,pins =
2062                                         <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
2063                                         <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
2064                         };
2065                 };
2066
2067                 i2c8 {
2068                         i2c8_xfer: i2c8-xfer {
2069                                 rockchip,pins =
2070                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
2071                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
2072                         };
2073                 };
2074
2075                 i2s0 {
2076                         i2s0_8ch_bus: i2s0-8ch-bus {
2077                                 rockchip,pins =
2078                                         <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
2079                                         <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
2080                                         <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
2081                                         <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
2082                                         <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>,
2083                                         <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>,
2084                                         <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>,
2085                                         <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>,
2086                                         <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
2087                         };
2088                 };
2089
2090                 i2s1 {
2091                         i2s1_2ch_bus: i2s1-2ch-bus {
2092                                 rockchip,pins =
2093                                         <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
2094                                         <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
2095                                         <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
2096                                         <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
2097                                         <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
2098                         };
2099                 };
2100
2101                 sdio0 {
2102                         sdio0_bus1: sdio0-bus1 {
2103                                 rockchip,pins =
2104                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2105                         };
2106
2107                         sdio0_bus4: sdio0-bus4 {
2108                                 rockchip,pins =
2109                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2110                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2111                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2112                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2113                         };
2114
2115                         sdio0_cmd: sdio0-cmd {
2116                                 rockchip,pins =
2117                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2118                         };
2119
2120                         sdio0_clk: sdio0-clk {
2121                                 rockchip,pins =
2122                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2123                         };
2124
2125                         sdio0_cd: sdio0-cd {
2126                                 rockchip,pins =
2127                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2128                         };
2129
2130                         sdio0_pwr: sdio0-pwr {
2131                                 rockchip,pins =
2132                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2133                         };
2134
2135                         sdio0_bkpwr: sdio0-bkpwr {
2136                                 rockchip,pins =
2137                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2138                         };
2139
2140                         sdio0_wp: sdio0-wp {
2141                                 rockchip,pins =
2142                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2143                         };
2144
2145                         sdio0_int: sdio0-int {
2146                                 rockchip,pins =
2147                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2148                         };
2149                 };
2150
2151                 sdmmc {
2152                         sdmmc_bus1: sdmmc-bus1 {
2153                                 rockchip,pins =
2154                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2155                         };
2156
2157                         sdmmc_bus4: sdmmc-bus4 {
2158                                 rockchip,pins =
2159                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2160                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2161                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2162                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2163                         };
2164
2165                         sdmmc_clk: sdmmc-clk {
2166                                 rockchip,pins =
2167                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2168                         };
2169
2170                         sdmmc_cmd: sdmmc-cmd {
2171                                 rockchip,pins =
2172                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2173                         };
2174
2175                         sdmmc_cd: sdmmc-cd {
2176                                 rockchip,pins =
2177                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2178                         };
2179
2180                         sdmmc_wp: sdmmc-wp {
2181                                 rockchip,pins =
2182                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2183                         };
2184                 };
2185
2186                 sleep {
2187                         ap_pwroff: ap-pwroff {
2188                                 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
2189                         };
2190
2191                         ddrio_pwroff: ddrio-pwroff {
2192                                 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
2193                         };
2194                 };
2195
2196                 spdif {
2197                         spdif_bus: spdif-bus {
2198                                 rockchip,pins =
2199                                         <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
2200                         };
2201
2202                         spdif_bus_1: spdif-bus-1 {
2203                                 rockchip,pins =
2204                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2205                         };
2206                 };
2207
2208                 spi0 {
2209                         spi0_clk: spi0-clk {
2210                                 rockchip,pins =
2211                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>;
2212                         };
2213                         spi0_cs0: spi0-cs0 {
2214                                 rockchip,pins =
2215                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
2216                         };
2217                         spi0_cs1: spi0-cs1 {
2218                                 rockchip,pins =
2219                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
2220                         };
2221                         spi0_tx: spi0-tx {
2222                                 rockchip,pins =
2223                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>;
2224                         };
2225                         spi0_rx: spi0-rx {
2226                                 rockchip,pins =
2227                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>;
2228                         };
2229                 };
2230
2231                 spi1 {
2232                         spi1_clk: spi1-clk {
2233                                 rockchip,pins =
2234                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
2235                         };
2236                         spi1_cs0: spi1-cs0 {
2237                                 rockchip,pins =
2238                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>;
2239                         };
2240                         spi1_rx: spi1-rx {
2241                                 rockchip,pins =
2242                                         <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
2243                         };
2244                         spi1_tx: spi1-tx {
2245                                 rockchip,pins =
2246                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
2247                         };
2248                 };
2249
2250                 spi2 {
2251                         spi2_clk: spi2-clk {
2252                                 rockchip,pins =
2253                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2254                         };
2255                         spi2_cs0: spi2-cs0 {
2256                                 rockchip,pins =
2257                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
2258                         };
2259                         spi2_rx: spi2-rx {
2260                                 rockchip,pins =
2261                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
2262                         };
2263                         spi2_tx: spi2-tx {
2264                                 rockchip,pins =
2265                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
2266                         };
2267                 };
2268
2269                 spi3 {
2270                         spi3_clk: spi3-clk {
2271                                 rockchip,pins =
2272                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>;
2273                         };
2274                         spi3_cs0: spi3-cs0 {
2275                                 rockchip,pins =
2276                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>;
2277                         };
2278                         spi3_rx: spi3-rx {
2279                                 rockchip,pins =
2280                                         <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>;
2281                         };
2282                         spi3_tx: spi3-tx {
2283                                 rockchip,pins =
2284                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>;
2285                         };
2286                 };
2287
2288                 spi4 {
2289                         spi4_clk: spi4-clk {
2290                                 rockchip,pins =
2291                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>;
2292                         };
2293                         spi4_cs0: spi4-cs0 {
2294                                 rockchip,pins =
2295                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>;
2296                         };
2297                         spi4_rx: spi4-rx {
2298                                 rockchip,pins =
2299                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>;
2300                         };
2301                         spi4_tx: spi4-tx {
2302                                 rockchip,pins =
2303                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>;
2304                         };
2305                 };
2306
2307                 spi5 {
2308                         spi5_clk: spi5-clk {
2309                                 rockchip,pins =
2310                                         <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>;
2311                         };
2312                         spi5_cs0: spi5-cs0 {
2313                                 rockchip,pins =
2314                                         <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
2315                         };
2316                         spi5_rx: spi5-rx {
2317                                 rockchip,pins =
2318                                         <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>;
2319                         };
2320                         spi5_tx: spi5-tx {
2321                                 rockchip,pins =
2322                                         <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>;
2323                         };
2324                 };
2325
2326                 tsadc {
2327                         otp_gpio: otp-gpio {
2328                                 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2329                         };
2330
2331                         otp_out: otp-out {
2332                                 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2333                         };
2334                 };
2335
2336                 uart0 {
2337                         uart0_xfer: uart0-xfer {
2338                                 rockchip,pins =
2339                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>,
2340                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
2341                         };
2342
2343                         uart0_cts: uart0-cts {
2344                                 rockchip,pins =
2345                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2346                         };
2347
2348                         uart0_rts: uart0-rts {
2349                                 rockchip,pins =
2350                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2351                         };
2352                 };
2353
2354                 uart1 {
2355                         uart1_xfer: uart1-xfer {
2356                                 rockchip,pins =
2357                                         <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>,
2358                                         <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
2359                         };
2360                 };
2361
2362                 uart2a {
2363                         uart2a_xfer: uart2a-xfer {
2364                                 rockchip,pins =
2365                                         <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>,
2366                                         <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
2367                         };
2368                 };
2369
2370                 uart2b {
2371                         uart2b_xfer: uart2b-xfer {
2372                                 rockchip,pins =
2373                                         <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>,
2374                                         <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
2375                         };
2376                 };
2377
2378                 uart2c {
2379                         uart2c_xfer: uart2c-xfer {
2380                                 rockchip,pins =
2381                                         <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>,
2382                                         <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
2383                         };
2384                 };
2385
2386                 uart3 {
2387                         uart3_xfer: uart3-xfer {
2388                                 rockchip,pins =
2389                                         <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>,
2390                                         <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>;
2391                         };
2392
2393                         uart3_cts: uart3-cts {
2394                                 rockchip,pins =
2395                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2396                         };
2397
2398                         uart3_rts: uart3-rts {
2399                                 rockchip,pins =
2400                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
2401                         };
2402                 };
2403
2404                 uart4 {
2405                         uart4_xfer: uart4-xfer {
2406                                 rockchip,pins =
2407                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>,
2408                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
2409                         };
2410                 };
2411
2412                 uarthdcp {
2413                         uarthdcp_xfer: uarthdcp-xfer {
2414                                 rockchip,pins =
2415                                         <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>,
2416                                         <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
2417                         };
2418                 };
2419
2420                 pwm0 {
2421                         pwm0_pin: pwm0-pin {
2422                                 rockchip,pins =
2423                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2424                         };
2425
2426                         vop0_pwm_pin: vop0-pwm-pin {
2427                                 rockchip,pins =
2428                                         <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2429                         };
2430                 };
2431
2432                 pwm1 {
2433                         pwm1_pin: pwm1-pin {
2434                                 rockchip,pins =
2435                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2436                         };
2437
2438                         vop1_pwm_pin: vop1-pwm-pin {
2439                                 rockchip,pins =
2440                                         <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2441                         };
2442                 };
2443
2444                 pwm2 {
2445                         pwm2_pin: pwm2-pin {
2446                                 rockchip,pins =
2447                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2448                         };
2449
2450                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2451                                 rockchip,pins =
2452                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
2453                         };
2454                 };
2455
2456                 pwm3a {
2457                         pwm3a_pin: pwm3a-pin {
2458                                 rockchip,pins =
2459                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2460                         };
2461                 };
2462
2463                 pwm3b {
2464                         pwm3b_pin: pwm3b-pin {
2465                                 rockchip,pins =
2466                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2467                         };
2468                 };
2469
2470                 hdmi {
2471                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2472                                 rockchip,pins =
2473                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2474                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2475                         };
2476
2477                         hdmi_cec: hdmi-cec {
2478                                 rockchip,pins =
2479                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2480                         };
2481                 };
2482
2483                 pcie {
2484                         pcie_clkreqn: pci-clkreqn {
2485                                 rockchip,pins =
2486                                         <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
2487                         };
2488
2489                         pcie_clkreqnb: pci-clkreqnb {
2490                                 rockchip,pins =
2491                                         <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
2492                         };
2493
2494                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2495                                 rockchip,pins =
2496                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2497                         };
2498
2499                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2500                                 rockchip,pins =
2501                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2502                         };
2503                 };
2504
2505         };
2506 };