arch/arm/dts/rk3399-gru.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Gru (and derivatives) board device tree source
   4  *
   5  * Copyright 2016-2017 Google, Inc
   6  */
   7
   8 #include <dt-bindings/input/input.h>
   9 #include "rk3399.dtsi"
  10 #include "rk3399-op1-opp.dtsi"
  11
  12 / {
  13         chosen {
  14                 stdout-path = "serial2:115200n8";
  15         };
  16
  17         /*
  18          * Power Tree
  19          *
  20          * In general an attempt is made to include all rails called out by
  21          * the schematic as long as those rails interact in some way with
  22          * the AP.  AKA:
  23          * - Rails that only connect to the EC (or devices that the EC talks to)
  24          *   are not included.
  25          * - Rails _are_ included if the rails go to the AP even if the AP
  26          *   doesn't currently care about them / they are always on.  The idea
  27          *   here is that it makes it easier to map to the schematic or extend
  28          *   later.
  29          *
  30          * If two rails are substantially the same from the AP's point of
  31          * view, though, we won't create a full fixed regulator.  We'll just
  32          * put the child rail as an alias of the parent rail.  Sometimes rails
  33          * look the same to the AP because one of these is true:
  34          * - The EC controls the enable and the EC always enables a rail as
  35          *   long as the AP is running.
  36          * - The rails are actually connected to each other by a jumper and
  37          *   the distinction is just there to add clarity/flexibility to the
  38          *   schematic.
  39          */
  40
  41         ppvar_sys: ppvar-sys {
  42                 compatible = "regulator-fixed";
  43                 regulator-name = "ppvar_sys";
  44                 regulator-always-on;
  45                 regulator-boot-on;
  46         };
  47
  48         pp1200_lpddr: pp1200-lpddr {
  49                 compatible = "regulator-fixed";
  50                 regulator-name = "pp1200_lpddr";
  51
  52                 /* EC turns on w/ lpddr_pwr_en; always on for AP */
  53                 regulator-always-on;
  54                 regulator-boot-on;
  55                 regulator-min-microvolt = <1200000>;
  56                 regulator-max-microvolt = <1200000>;
  57
  58                 vin-supply = <&ppvar_sys>;
  59         };
  60
  61         pp1800: pp1800 {
  62                 compatible = "regulator-fixed";
  63                 regulator-name = "pp1800";
  64
  65                 /* Always on when ppvar_sys shows power good */
  66                 regulator-always-on;
  67                 regulator-boot-on;
  68                 regulator-min-microvolt = <1800000>;
  69                 regulator-max-microvolt = <1800000>;
  70
  71                 vin-supply = <&ppvar_sys>;
  72         };
  73
  74         pp3300: pp3300 {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "pp3300";
  77
  78                 /* Always on; plain and simple */
  79                 regulator-always-on;
  80                 regulator-boot-on;
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83
  84                 vin-supply = <&ppvar_sys>;
  85         };
  86
  87         pp5000: pp5000 {
  88                 compatible = "regulator-fixed";
  89                 regulator-name = "pp5000";
  90
  91                 /* EC turns on w/ pp5000_en; always on for AP */
  92                 regulator-always-on;
  93                 regulator-boot-on;
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96
  97                 vin-supply = <&ppvar_sys>;
  98         };
  99
 100         ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
 101                 compatible = "pwm-regulator";
 102                 regulator-name = "ppvar_bigcpu_pwm";
 103
 104                 pwms = <&pwm1 0 3337 0>;
 105                 pwm-supply = <&ppvar_sys>;
 106                 pwm-dutycycle-range = <100 0>;
 107                 pwm-dutycycle-unit = <100>;
 108
 109                 /* EC turns on w/ ap_core_en; always on for AP */
 110                 regulator-always-on;
 111                 regulator-boot-on;
 112                 regulator-min-microvolt = <800107>;
 113                 regulator-max-microvolt = <1302232>;
 114         };
 115
 116         ppvar_bigcpu: ppvar-bigcpu {
 117                 compatible = "vctrl-regulator";
 118                 regulator-name = "ppvar_bigcpu";
 119
 120                 regulator-min-microvolt = <800107>;
 121                 regulator-max-microvolt = <1302232>;
 122
 123                 ctrl-supply = <&ppvar_bigcpu_pwm>;
 124                 ctrl-voltage-range = <800107 1302232>;
 125
 126                 regulator-settling-time-up-us = <322>;
 127         };
 128
 129         ppvar_litcpu_pwm: ppvar-litcpu-pwm {
 130                 compatible = "pwm-regulator";
 131                 regulator-name = "ppvar_litcpu_pwm";
 132
 133                 pwms = <&pwm2 0 3337 0>;
 134                 pwm-supply = <&ppvar_sys>;
 135                 pwm-dutycycle-range = <100 0>;
 136                 pwm-dutycycle-unit = <100>;
 137
 138                 /* EC turns on w/ ap_core_en; always on for AP */
 139                 regulator-always-on;
 140                 regulator-boot-on;
 141                 regulator-min-microvolt = <797743>;
 142                 regulator-max-microvolt = <1307837>;
 143         };
 144
 145         ppvar_litcpu: ppvar-litcpu {
 146                 compatible = "vctrl-regulator";
 147                 regulator-name = "ppvar_litcpu";
 148
 149                 regulator-min-microvolt = <797743>;
 150                 regulator-max-microvolt = <1307837>;
 151
 152                 ctrl-supply = <&ppvar_litcpu_pwm>;
 153                 ctrl-voltage-range = <797743 1307837>;
 154
 155                 regulator-settling-time-up-us = <384>;
 156         };
 157
 158         ppvar_gpu_pwm: ppvar-gpu-pwm {
 159                 compatible = "pwm-regulator";
 160                 regulator-name = "ppvar_gpu_pwm";
 161
 162                 pwms = <&pwm0 0 3337 0>;
 163                 pwm-supply = <&ppvar_sys>;
 164                 pwm-dutycycle-range = <100 0>;
 165                 pwm-dutycycle-unit = <100>;
 166
 167                 /* EC turns on w/ ap_core_en; always on for AP */
 168                 regulator-always-on;
 169                 regulator-boot-on;
 170                 regulator-min-microvolt = <786384>;
 171                 regulator-max-microvolt = <1217747>;
 172         };
 173
 174         ppvar_gpu: ppvar-gpu {
 175                 compatible = "vctrl-regulator";
 176                 regulator-name = "ppvar_gpu";
 177
 178                 regulator-min-microvolt = <786384>;
 179                 regulator-max-microvolt = <1217747>;
 180
 181                 ctrl-supply = <&ppvar_gpu_pwm>;
 182                 ctrl-voltage-range = <786384 1217747>;
 183
 184                 regulator-settling-time-up-us = <390>;
 185         };
 186
 187         /* EC turns on w/ pp900_ddrpll_en */
 188         pp900_ddrpll: pp900-ap {
 189         };
 190
 191         /* EC turns on w/ pp900_pll_en */
 192         pp900_pll: pp900-ap {
 193         };
 194
 195         /* EC turns on w/ pp900_pmu_en */
 196         pp900_pmu: pp900-ap {
 197         };
 198
 199         /* EC turns on w/ pp1800_s0_en_l */
 200         pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
 201         };
 202
 203         /* EC turns on w/ pp1800_avdd_en_l */
 204         pp1800_avdd: pp1800 {
 205         };
 206
 207         /* EC turns on w/ pp1800_lid_en_l */
 208         pp1800_lid: pp1800_mic: pp1800 {
 209         };
 210
 211         /* EC turns on w/ lpddr_pwr_en */
 212         pp1800_lpddr: pp1800 {
 213         };
 214
 215         /* EC turns on w/ pp1800_pmu_en_l */
 216         pp1800_pmu: pp1800 {
 217         };
 218
 219         /* EC turns on w/ pp1800_usb_en_l */
 220         pp1800_usb: pp1800 {
 221         };
 222
 223         pp3000_sd_slot: pp3000-sd-slot {
 224                 compatible = "regulator-fixed";
 225                 regulator-name = "pp3000_sd_slot";
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&sd_slot_pwr_en>;
 228
 229                 enable-active-high;
 230                 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 231
 232                 vin-supply = <&pp3000>;
 233         };
 234
 235         /*
 236          * Technically, this is a small abuse of 'regulator-gpio'; this
 237          * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
 238          * always on though, so it is sufficient to simply control the mux
 239          * here.
 240          */
 241         ppvar_sd_card_io: ppvar-sd-card-io {
 242                 compatible = "regulator-gpio";
 243                 regulator-name = "ppvar_sd_card_io";
 244                 pinctrl-names = "default";
 245                 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
 246
 247                 enable-active-high;
 248                 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
 249                 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
 250                 states = <1800000 0x1
 251                           3000000 0x0>;
 252
 253                 regulator-min-microvolt = <1800000>;
 254                 regulator-max-microvolt = <3000000>;
 255         };
 256
 257         /* EC turns on w/ pp3300_trackpad_en_l */
 258         pp3300_trackpad: pp3300-trackpad {
 259         };
 260
 261         /* EC turns on w/ usb_a_en */
 262         pp5000_usb_a_vbus: pp5000 {
 263         };
 264
 265         ap_rtc_clk: ap-rtc-clk {
 266                 compatible = "fixed-clock";
 267                 clock-frequency = <32768>;
 268                 clock-output-names = "xin32k";
 269                 #clock-cells = <0>;
 270         };
 271
 272         max98357a: max98357a {
 273                 compatible = "maxim,max98357a";
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&sdmode_en>;
 276                 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 277                 sdmode-delay = <2>;
 278                 #sound-dai-cells = <0>;
 279                 status = "okay";
 280         };
 281
 282         sound: sound {
 283                 compatible = "rockchip,rk3399-gru-sound";
 284                 rockchip,cpu = <&i2s0 &i2s2>;
 285         };
 286 };
 287
 288 &cdn_dp {
 289         status = "okay";
 290 };
 291
 292 /*
 293  * Set some suspend operating points to avoid OVP in suspend
 294  *
 295  * When we go into S3 ARM Trusted Firmware will transition our PWM regulators
 296  * from wherever they're at back to the "default" operating point (whatever
 297  * voltage we get when we set the PWM pins to "input").
 298  *
 299  * This quick transition under light load has the possibility to trigger the
 300  * regulator "over voltage protection" (OVP).
 301  *
 302  * To make extra certain that we don't hit this OVP at suspend time, we'll
 303  * transition to a voltage that's much closer to the default (~1.0 V) so that
 304  * there will not be a big jump.  Technically we only need to get within 200 mV
 305  * of the default voltage, but the speed here should be fast enough and we need
 306  * suspend/resume to be rock solid.
 307  */
 308
 309 &cluster0_opp {
 310         opp05 {
 311                 opp-suspend;
 312         };
 313 };
 314
 315 &cluster1_opp {
 316         opp06 {
 317                 opp-suspend;
 318         };
 319 };
 320
 321 &cpu_l0 {
 322         cpu-supply = <&ppvar_litcpu>;
 323 };
 324
 325 &cpu_l1 {
 326         cpu-supply = <&ppvar_litcpu>;
 327 };
 328
 329 &cpu_l2 {
 330         cpu-supply = <&ppvar_litcpu>;
 331 };
 332
 333 &cpu_l3 {
 334         cpu-supply = <&ppvar_litcpu>;
 335 };
 336
 337 &cpu_b0 {
 338         cpu-supply = <&ppvar_bigcpu>;
 339 };
 340
 341 &cpu_b1 {
 342         cpu-supply = <&ppvar_bigcpu>;
 343 };
 344
 345 &cru {
 346         assigned-clocks =
 347                 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 348                 <&cru PLL_NPLL>,
 349                 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 350                 <&cru PCLK_PERIHP>,
 351                 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 352                 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 353                 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
 354                 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
 355                 <&cru ACLK_GIC_PRE>,
 356                 <&cru PCLK_DDR>;
 357         assigned-clock-rates =
 358                 <600000000>, <800000000>,
 359                 <1000000000>,
 360                 <150000000>, <75000000>,
 361                 <37500000>,
 362                 <100000000>, <100000000>,
 363                 <50000000>, <800000000>,
 364                 <100000000>, <50000000>,
 365                 <400000000>, <400000000>,
 366                 <200000000>,
 367                 <200000000>;
 368 };
 369
 370 &emmc_phy {
 371         status = "okay";
 372 };
 373
 374 &gpu {
 375         mali-supply = <&ppvar_gpu>;
 376         status = "okay";
 377 };
 378
 379 ap_i2c_ts: &i2c3 {
 380         status = "okay";
 381
 382         clock-frequency = <400000>;
 383
 384         /* These are relatively safe rise/fall times */
 385         i2c-scl-falling-time-ns = <50>;
 386         i2c-scl-rising-time-ns = <300>;
 387 };
 388
 389 ap_i2c_audio: &i2c8 {
 390         status = "okay";
 391
 392         clock-frequency = <400000>;
 393
 394         /* These are relatively safe rise/fall times */
 395         i2c-scl-falling-time-ns = <50>;
 396         i2c-scl-rising-time-ns = <300>;
 397
 398         codec: da7219@1a {
 399                 compatible = "dlg,da7219";
 400                 reg = <0x1a>;
 401                 interrupt-parent = <&gpio1>;
 402                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 403                 clocks = <&cru SCLK_I2S_8CH_OUT>;
 404                 clock-names = "mclk";
 405                 dlg,micbias-lvl = <2600>;
 406                 dlg,mic-amp-in-sel = "diff";
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&headset_int_l>;
 409                 VDD-supply = <&pp1800>;
 410                 VDDMIC-supply = <&pp3300>;
 411                 VDDIO-supply = <&pp1800>;
 412
 413                 da7219_aad {
 414                         dlg,adc-1bit-rpt = <1>;
 415                         dlg,btn-avg = <4>;
 416                         dlg,btn-cfg = <50>;
 417                         dlg,mic-det-thr = <500>;
 418                         dlg,jack-ins-deb = <20>;
 419                         dlg,jack-det-rate = "32ms_64ms";
 420                         dlg,jack-rem-deb = <1>;
 421
 422                         dlg,a-d-btn-thr = <0xa>;
 423                         dlg,d-b-btn-thr = <0x16>;
 424                         dlg,b-c-btn-thr = <0x21>;
 425                         dlg,c-mic-btn-thr = <0x3E>;
 426                 };
 427         };
 428 };
 429
 430 &i2s0 {
 431         status = "okay";
 432 };
 433
 434 &i2s2 {
 435         status = "okay";
 436 };
 437
 438 &io_domains {
 439         status = "okay";
 440
 441         audio-supply = <&pp1800_audio>;         /* APIO5_VDD;  3d 4a */
 442         bt656-supply = <&pp1800_ap_io>;         /* APIO2_VDD;  2a 2b */
 443         gpio1830-supply = <&pp3000_ap>;         /* APIO4_VDD;  4c 4d */
 444         sdmmc-supply = <&ppvar_sd_card_io>;     /* SDMMC0_VDD; 4b    */
 445 };
 446
 447 &pcie0 {
 448         status = "okay";
 449
 450         ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
 453         vpcie3v3-supply = <&pp3300_wifi_bt>;
 454         vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
 455         vpcie0v9-supply = <&pp900_pcie>;
 456
 457         pci_rootport: pcie@0,0 {
 458                 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
 459                 #address-cells = <3>;
 460                 #size-cells = <2>;
 461                 ranges;
 462         };
 463 };
 464
 465 &pcie_phy {
 466         status = "okay";
 467 };
 468
 469 &pmu_io_domains {
 470         status = "okay";
 471
 472         pmu1830-supply = <&pp1800_pmu>;         /* PMUIO2_VDD */
 473 };
 474
 475 &pwm0 {
 476         status = "okay";
 477 };
 478
 479 &pwm1 {
 480         status = "okay";
 481 };
 482
 483 &pwm2 {
 484         status = "okay";
 485 };
 486
 487 &pwm3 {
 488         status = "okay";
 489 };
 490
 491 &sdhci {
 492         /*
 493          * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
 494          * same (or nearly the same) performance for all eMMC that are intended
 495          * to be used.
 496          */
 497         assigned-clock-rates = <150000000>;
 498
 499         bus-width = <8>;
 500         mmc-hs400-1_8v;
 501         mmc-hs400-enhanced-strobe;
 502         non-removable;
 503         status = "okay";
 504 };
 505
 506 &sdmmc {
 507         status = "okay";
 508
 509         /*
 510          * Note: configure "sdmmc_cd" as card detect even though it's actually
 511          * hooked to ground.  Because we specified "cd-gpios" below dw_mmc
 512          * should be ignoring card detect anyway.  Specifying the pin as
 513          * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
 514          * turned on that the system will still make sure the port is
 515          * configured as SDMMC and not JTAG.
 516          */
 517         pinctrl-names = "default";
 518         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
 519                      &sdmmc_bus4>;
 520
 521         bus-width = <4>;
 522         cap-mmc-highspeed;
 523         cap-sd-highspeed;
 524         cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 525         disable-wp;
 526         sd-uhs-sdr12;
 527         sd-uhs-sdr25;
 528         sd-uhs-sdr50;
 529         sd-uhs-sdr104;
 530         vmmc-supply = <&pp3000_sd_slot>;
 531         vqmmc-supply = <&ppvar_sd_card_io>;
 532 };
 533
 534 &spi1 {
 535         status = "okay";
 536
 537         pinctrl-names = "default", "sleep";
 538         pinctrl-1 = <&spi1_sleep>;
 539
 540         spiflash@0 {
 541                 compatible = "jedec,spi-nor";
 542                 reg = <0>;
 543
 544                 /* May run faster once verified. */
 545                 spi-max-frequency = <10000000>;
 546         };
 547 };
 548
 549 &spi2 {
 550         status = "okay";
 551 };
 552
 553 &spi5 {
 554         status = "okay";
 555
 556         cros_ec: ec@0 {
 557                 compatible = "google,cros-ec-spi";
 558                 reg = <0>;
 559                 interrupt-parent = <&gpio0>;
 560                 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&ec_ap_int_l>;
 563                 spi-max-frequency = <3000000>;
 564
 565                 i2c_tunnel: i2c-tunnel {
 566                         compatible = "google,cros-ec-i2c-tunnel";
 567                         google,remote-bus = <4>;
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                 };
 571
 572                 usbc_extcon0: extcon0 {
 573                         compatible = "google,extcon-usbc-cros-ec";
 574                         google,usb-port-id = <0>;
 575                 };
 576         };
 577 };
 578
 579 &tsadc {
 580         status = "okay";
 581
 582         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 583         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 584 };
 585
 586 &tcphy0 {
 587         status = "okay";
 588         extcon = <&usbc_extcon0>;
 589 };
 590
 591 &u2phy0 {
 592         status = "okay";
 593 };
 594
 595 &u2phy0_host {
 596         status = "okay";
 597 };
 598
 599 &u2phy1_host {
 600         status = "okay";
 601 };
 602
 603 &u2phy0_otg {
 604         status = "okay";
 605 };
 606
 607 &u2phy1_otg {
 608         status = "okay";
 609 };
 610
 611 &uart2 {
 612         status = "okay";
 613 };
 614
 615 &usb_host0_ohci {
 616         status = "okay";
 617 };
 618
 619 &usbdrd3_0 {
 620         status = "okay";
 621         extcon = <&usbc_extcon0>;
 622 };
 623
 624 &usbdrd_dwc3_0 {
 625         status = "okay";
 626         dr_mode = "host";
 627 };
 628
 629 &vopb {
 630         status = "okay";
 631 };
 632
 633 &vopb_mmu {
 634         status = "okay";
 635 };
 636
 637 &vopl {
 638         status = "okay";
 639 };
 640
 641 &vopl_mmu {
 642         status = "okay";
 643 };
 644
 645 #include <cros-ec-keyboard.dtsi>
 646 #include <cros-ec-sbs.dtsi>
 647
 648 &pinctrl {
 649         /*
 650          * pinctrl settings for pins that have no real owners.
 651          *
 652          * At the moment settings are identical for S0 and S3, but if we later
 653          * need to configure things differently for S3 we'll adjust here.
 654          */
 655         pinctrl-names = "default";
 656         pinctrl-0 = <
 657                 &ap_pwroff      /* AP will auto-assert this when in S3 */
 658                 &clk_32k        /* This pin is always 32k on gru boards */
 659         >;
 660
 661         pcfg_output_low: pcfg-output-low {
 662                 output-low;
 663         };
 664
 665         pcfg_output_high: pcfg-output-high {
 666                 output-high;
 667         };
 668
 669         pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 670                 bias-disable;
 671                 drive-strength = <8>;
 672         };
 673
 674         backlight-enable {
 675                 bl_en: bl-en {
 676                         rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
 677                 };
 678         };
 679
 680         cros-ec {
 681                 ec_ap_int_l: ec-ap-int-l {
 682                         rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
 683                 };
 684         };
 685
 686         discrete-regulators {
 687                 sd_io_pwr_en: sd-io-pwr-en {
 688                         rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
 689                                          &pcfg_pull_none>;
 690                 };
 691
 692                 sd_pwr_1800_sel: sd-pwr-1800-sel {
 693                         rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
 694                                          &pcfg_pull_none>;
 695                 };
 696
 697                 sd_slot_pwr_en: sd-slot-pwr-en {
 698                         rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
 699                                          &pcfg_pull_none>;
 700                 };
 701         };
 702
 703         codec {
 704                 /* Has external pullup */
 705                 headset_int_l: headset-int-l {
 706                         rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
 707                 };
 708
 709                 mic_int: mic-int {
 710                         rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
 711                 };
 712         };
 713
 714         max98357a {
 715                 sdmode_en: sdmode-en {
 716                         rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
 717                 };
 718         };
 719
 720         pcie {
 721                 pcie_clkreqn_cpm: pci-clkreqn-cpm {
 722                         /*
 723                          * Since our pcie doesn't support ClockPM(CPM), we want
 724                          * to hack this as gpio, so the EP could be able to
 725                          * de-assert it along and make ClockPM(CPM) work.
 726                          */
 727                         rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 728                 };
 729         };
 730
 731         sdmmc {
 732                 /*
 733                  * We run sdmmc at max speed; bump up drive strength.
 734                  * We also have external pulls, so disable the internal ones.
 735                  */
 736                 sdmmc_bus4: sdmmc-bus4 {
 737                         rockchip,pins =
 738                                 <4 RK_PB0 1 &pcfg_pull_none_8ma>,
 739                                 <4 RK_PB1 1 &pcfg_pull_none_8ma>,
 740                                 <4 RK_PB2 1 &pcfg_pull_none_8ma>,
 741                                 <4 RK_PB3 1 &pcfg_pull_none_8ma>;
 742                 };
 743
 744                 sdmmc_clk: sdmmc-clk {
 745                         rockchip,pins =
 746                                 <4 RK_PB4 1 &pcfg_pull_none_8ma>;
 747                 };
 748
 749                 sdmmc_cmd: sdmmc-cmd {
 750                         rockchip,pins =
 751                                 <4 RK_PB5 1 &pcfg_pull_none_8ma>;
 752                 };
 753
 754                 /*
 755                  * In our case the official card detect is hooked to ground
 756                  * to avoid getting access to JTAG just by sticking something
 757                  * in the SD card slot (see the force_jtag bit in the TRM).
 758                  *
 759                  * We still configure it as card detect because it doesn't
 760                  * hurt and dw_mmc will ignore it.  We make sure to disable
 761                  * the pull though so we don't burn needless power.
 762                  */
 763                 sdmmc_cd: sdmmc-cd {
 764                         rockchip,pins =
 765                                 <0 RK_PA7 1 &pcfg_pull_none>;
 766                 };
 767
 768                 /* This is where we actually hook up CD; has external pull */
 769                 sdmmc_cd_gpio: sdmmc-cd-gpio {
 770                         rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 771                 };
 772         };
 773
 774         spi1 {
 775                 spi1_sleep: spi1-sleep {
 776                         /*
 777                          * Pull down SPI1 CLK/CS/RX/TX during suspend, to
 778                          * prevent leakage.
 779                          */
 780                         rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
 781                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
 782                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
 783                                         <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
 784                 };
 785         };
 786
 787         touchscreen {
 788                 touch_int_l: touch-int-l {
 789                         rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
 790                 };
 791
 792                 touch_reset_l: touch-reset-l {
 793                         rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 794                 };
 795         };
 796
 797         trackpad {
 798                 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
 799                         rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
 800                 };
 801
 802                 trackpad_int_l: trackpad-int-l {
 803                         rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
 804                 };
 805         };
 806
 807         wifi: wifi {
 808                 wlan_module_reset_l: wlan-module-reset-l {
 809                         rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
 810                 };
 811
 812                 bt_host_wake_l: bt-host-wake-l {
 813                         /* Kevin has an external pull up, but Gru does not */
 814                         rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
 815                 };
 816         };
 817
 818         write-protect {
 819                 ap_fw_wp: ap-fw-wp {
 820                         rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 821                 };
 822         };
 823 };