arch/arm/dts/r8a77995.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77995 SoC
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  * Copyright (C) 2017 Glider bvba
   7  */
   8
   9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/r8a77995-sysc.h>
  12
  13 / {
  14         compatible = "renesas,r8a77995";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         /* External CAN clock - to be overridden by boards that provide it */
  19         can_clk: can {
  20                 compatible = "fixed-clock";
  21                 #clock-cells = <0>;
  22                 clock-frequency = <0>;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 a53_0: cpu@0 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         reg = <0x0>;
  32                         device_type = "cpu";
  33                         power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
  34                         next-level-cache = <&L2_CA53>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 L2_CA53: cache-controller-1 {
  39                         compatible = "cache";
  40                         power-domains = <&sysc R8A77995_PD_CA53_SCU>;
  41                         cache-unified;
  42                         cache-level = <2>;
  43                 };
  44         };
  45
  46         extal_clk: extal {
  47                 compatible = "fixed-clock";
  48                 #clock-cells = <0>;
  49                 /* This value must be overridden by the board */
  50                 clock-frequency = <0>;
  51         };
  52
  53         pmu_a53 {
  54                 compatible = "arm,cortex-a53-pmu";
  55                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  56         };
  57
  58         psci {
  59                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  60                 method = "smc";
  61         };
  62
  63         scif_clk: scif {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <0>;
  67         };
  68
  69         soc: soc {
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&gic>;
  72                 #address-cells = <2>;
  73                 #size-cells = <2>;
  74                 ranges;
  75
  76                 rwdt: watchdog@e6020000 {
  77                         compatible = "renesas,r8a77995-wdt",
  78                                      "renesas,rcar-gen3-wdt";
  79                         reg = <0 0xe6020000 0 0x0c>;
  80                         clocks = <&cpg CPG_MOD 402>;
  81                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
  82                         resets = <&cpg 402>;
  83                         status = "disabled";
  84                 };
  85
  86                 gpio0: gpio@e6050000 {
  87                         compatible = "renesas,gpio-r8a77995",
  88                                      "renesas,rcar-gen3-gpio";
  89                         reg = <0 0xe6050000 0 0x50>;
  90                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  91                         #gpio-cells = <2>;
  92                         gpio-controller;
  93                         gpio-ranges = <&pfc 0 0 9>;
  94                         #interrupt-cells = <2>;
  95                         interrupt-controller;
  96                         clocks = <&cpg CPG_MOD 912>;
  97                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
  98                         resets = <&cpg 912>;
  99                 };
 100
 101                 gpio1: gpio@e6051000 {
 102                         compatible = "renesas,gpio-r8a77995",
 103                                      "renesas,rcar-gen3-gpio";
 104                         reg = <0 0xe6051000 0 0x50>;
 105                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 106                         #gpio-cells = <2>;
 107                         gpio-controller;
 108                         gpio-ranges = <&pfc 0 32 32>;
 109                         #interrupt-cells = <2>;
 110                         interrupt-controller;
 111                         clocks = <&cpg CPG_MOD 911>;
 112                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 113                         resets = <&cpg 911>;
 114                 };
 115
 116                 gpio2: gpio@e6052000 {
 117                         compatible = "renesas,gpio-r8a77995",
 118                                      "renesas,rcar-gen3-gpio";
 119                         reg = <0 0xe6052000 0 0x50>;
 120                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 121                         #gpio-cells = <2>;
 122                         gpio-controller;
 123                         gpio-ranges = <&pfc 0 64 32>;
 124                         #interrupt-cells = <2>;
 125                         interrupt-controller;
 126                         clocks = <&cpg CPG_MOD 910>;
 127                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 128                         resets = <&cpg 910>;
 129                 };
 130
 131                 gpio3: gpio@e6053000 {
 132                         compatible = "renesas,gpio-r8a77995",
 133                                      "renesas,rcar-gen3-gpio";
 134                         reg = <0 0xe6053000 0 0x50>;
 135                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 136                         #gpio-cells = <2>;
 137                         gpio-controller;
 138                         gpio-ranges = <&pfc 0 96 10>;
 139                         #interrupt-cells = <2>;
 140                         interrupt-controller;
 141                         clocks = <&cpg CPG_MOD 909>;
 142                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 143                         resets = <&cpg 909>;
 144                 };
 145
 146                 gpio4: gpio@e6054000 {
 147                         compatible = "renesas,gpio-r8a77995",
 148                                      "renesas,rcar-gen3-gpio";
 149                         reg = <0 0xe6054000 0 0x50>;
 150                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 151                         #gpio-cells = <2>;
 152                         gpio-controller;
 153                         gpio-ranges = <&pfc 0 128 32>;
 154                         #interrupt-cells = <2>;
 155                         interrupt-controller;
 156                         clocks = <&cpg CPG_MOD 908>;
 157                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 158                         resets = <&cpg 908>;
 159                 };
 160
 161                 gpio5: gpio@e6055000 {
 162                         compatible = "renesas,gpio-r8a77995",
 163                                      "renesas,rcar-gen3-gpio";
 164                         reg = <0 0xe6055000 0 0x50>;
 165                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 166                         #gpio-cells = <2>;
 167                         gpio-controller;
 168                         gpio-ranges = <&pfc 0 160 21>;
 169                         #interrupt-cells = <2>;
 170                         interrupt-controller;
 171                         clocks = <&cpg CPG_MOD 907>;
 172                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 173                         resets = <&cpg 907>;
 174                 };
 175
 176                 gpio6: gpio@e6055400 {
 177                         compatible = "renesas,gpio-r8a77995",
 178                                      "renesas,rcar-gen3-gpio";
 179                         reg = <0 0xe6055400 0 0x50>;
 180                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 181                         #gpio-cells = <2>;
 182                         gpio-controller;
 183                         gpio-ranges = <&pfc 0 192 14>;
 184                         #interrupt-cells = <2>;
 185                         interrupt-controller;
 186                         clocks = <&cpg CPG_MOD 906>;
 187                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 188                         resets = <&cpg 906>;
 189                 };
 190
 191                 pfc: pin-controller@e6060000 {
 192                         compatible = "renesas,pfc-r8a77995";
 193                         reg = <0 0xe6060000 0 0x508>;
 194                 };
 195
 196                 cpg: clock-controller@e6150000 {
 197                         compatible = "renesas,r8a77995-cpg-mssr";
 198                         reg = <0 0xe6150000 0 0x1000>;
 199                         clocks = <&extal_clk>;
 200                         clock-names = "extal";
 201                         #clock-cells = <2>;
 202                         #power-domain-cells = <0>;
 203                         #reset-cells = <1>;
 204                 };
 205
 206                 rst: reset-controller@e6160000 {
 207                         compatible = "renesas,r8a77995-rst";
 208                         reg = <0 0xe6160000 0 0x0200>;
 209                 };
 210
 211                 sysc: system-controller@e6180000 {
 212                         compatible = "renesas,r8a77995-sysc";
 213                         reg = <0 0xe6180000 0 0x0400>;
 214                         #power-domain-cells = <1>;
 215                 };
 216
 217                 thermal: thermal@e6190000 {
 218                         compatible = "renesas,thermal-r8a77995";
 219                         reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
 220                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 223                         clocks = <&cpg CPG_MOD 522>;
 224                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 225                         resets = <&cpg 522>;
 226                         #thermal-sensor-cells = <0>;
 227                 };
 228
 229                 intc_ex: interrupt-controller@e61c0000 {
 230                         compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
 231                         #interrupt-cells = <2>;
 232                         interrupt-controller;
 233                         reg = <0 0xe61c0000 0 0x200>;
 234                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 235                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 236                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 237                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 238                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 239                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 240                         clocks = <&cpg CPG_MOD 407>;
 241                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 242                         resets = <&cpg 407>;
 243                 };
 244
 245                 hscif0: serial@e6540000 {
 246                         compatible = "renesas,hscif-r8a77995",
 247                                      "renesas,rcar-gen3-hscif",
 248                                      "renesas,hscif";
 249                         reg = <0 0xe6540000 0 0x60>;
 250                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 251                         clocks = <&cpg CPG_MOD 520>,
 252                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 253                                  <&scif_clk>;
 254                         clock-names = "fck", "brg_int", "scif_clk";
 255                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 256                                <&dmac2 0x31>, <&dmac2 0x30>;
 257                         dma-names = "tx", "rx", "tx", "rx";
 258                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 259                         resets = <&cpg 520>;
 260                         status = "disabled";
 261                 };
 262
 263                 hscif3: serial@e66a0000 {
 264                         compatible = "renesas,hscif-r8a77995",
 265                                      "renesas,rcar-gen3-hscif",
 266                                      "renesas,hscif";
 267                         reg = <0 0xe66a0000 0 0x60>;
 268                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&cpg CPG_MOD 517>,
 270                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 271                                  <&scif_clk>;
 272                         clock-names = "fck", "brg_int", "scif_clk";
 273                         dmas = <&dmac0 0x37>, <&dmac0 0x36>;
 274                         dma-names = "tx", "rx";
 275                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 276                         resets = <&cpg 517>;
 277                         status = "disabled";
 278                 };
 279
 280                 i2c0: i2c@e6500000 {
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         compatible = "renesas,i2c-r8a77995",
 284                                      "renesas,rcar-gen3-i2c";
 285                         reg = <0 0xe6500000 0 0x40>;
 286                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&cpg CPG_MOD 931>;
 288                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 289                         resets = <&cpg 931>;
 290                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 291                                <&dmac2 0x91>, <&dmac2 0x90>;
 292                         dma-names = "tx", "rx", "tx", "rx";
 293                         i2c-scl-internal-delay-ns = <6>;
 294                         status = "disabled";
 295                 };
 296
 297                 i2c1: i2c@e6508000 {
 298                         #address-cells = <1>;
 299                         #size-cells = <0>;
 300                         compatible = "renesas,i2c-r8a77995",
 301                                      "renesas,rcar-gen3-i2c";
 302                         reg = <0 0xe6508000 0 0x40>;
 303                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&cpg CPG_MOD 930>;
 305                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 306                         resets = <&cpg 930>;
 307                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 308                                <&dmac2 0x93>, <&dmac2 0x92>;
 309                         dma-names = "tx", "rx", "tx", "rx";
 310                         i2c-scl-internal-delay-ns = <6>;
 311                         status = "disabled";
 312                 };
 313
 314                 i2c2: i2c@e6510000 {
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                         compatible = "renesas,i2c-r8a77995",
 318                                      "renesas,rcar-gen3-i2c";
 319                         reg = <0 0xe6510000 0 0x40>;
 320                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&cpg CPG_MOD 929>;
 322                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 323                         resets = <&cpg 929>;
 324                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 325                                <&dmac2 0x95>, <&dmac2 0x94>;
 326                         dma-names = "tx", "rx", "tx", "rx";
 327                         i2c-scl-internal-delay-ns = <6>;
 328                         status = "disabled";
 329                 };
 330
 331                 i2c3: i2c@e66d0000 {
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         compatible = "renesas,i2c-r8a77995",
 335                                      "renesas,rcar-gen3-i2c";
 336                         reg = <0 0xe66d0000 0 0x40>;
 337                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&cpg CPG_MOD 928>;
 339                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 340                         resets = <&cpg 928>;
 341                         dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 342                         dma-names = "tx", "rx";
 343                         i2c-scl-internal-delay-ns = <6>;
 344                         status = "disabled";
 345                 };
 346
 347                 canfd: can@e66c0000 {
 348                         compatible = "renesas,r8a77995-canfd",
 349                                      "renesas,rcar-gen3-canfd";
 350                         reg = <0 0xe66c0000 0 0x8000>;
 351                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 352                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 353                         clocks = <&cpg CPG_MOD 914>,
 354                                <&cpg CPG_CORE R8A77995_CLK_CANFD>,
 355                                <&can_clk>;
 356                         clock-names = "fck", "canfd", "can_clk";
 357                         assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
 358                         assigned-clock-rates = <40000000>;
 359                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 360                         resets = <&cpg 914>;
 361                         status = "disabled";
 362
 363                         channel0 {
 364                                 status = "disabled";
 365                         };
 366
 367                         channel1 {
 368                                 status = "disabled";
 369                         };
 370                 };
 371
 372                 dmac0: dma-controller@e6700000 {
 373                         compatible = "renesas,dmac-r8a77995",
 374                                      "renesas,rcar-dmac";
 375                         reg = <0 0xe6700000 0 0x10000>;
 376                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
 377                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 378                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 379                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 380                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 381                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 382                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 383                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 384                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 385                         interrupt-names = "error",
 386                                         "ch0", "ch1", "ch2", "ch3",
 387                                         "ch4", "ch5", "ch6", "ch7";
 388                         clocks = <&cpg CPG_MOD 219>;
 389                         clock-names = "fck";
 390                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 391                         resets = <&cpg 219>;
 392                         #dma-cells = <1>;
 393                         dma-channels = <8>;
 394                 };
 395
 396                 dmac1: dma-controller@e7300000 {
 397                         compatible = "renesas,dmac-r8a77995",
 398                                      "renesas,rcar-dmac";
 399                         reg = <0 0xe7300000 0 0x10000>;
 400                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 401                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 402                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 403                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 404                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 405                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 406                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 407                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 408                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 409                         interrupt-names = "error",
 410                                         "ch0", "ch1", "ch2", "ch3",
 411                                         "ch4", "ch5", "ch6", "ch7";
 412                         clocks = <&cpg CPG_MOD 218>;
 413                         clock-names = "fck";
 414                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 415                         resets = <&cpg 218>;
 416                         #dma-cells = <1>;
 417                         dma-channels = <8>;
 418                 };
 419
 420                 dmac2: dma-controller@e7310000 {
 421                         compatible = "renesas,dmac-r8a77995",
 422                                      "renesas,rcar-dmac";
 423                         reg = <0 0xe7310000 0 0x10000>;
 424                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
 425                                       GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
 426                                       GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
 427                                       GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
 428                                       GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
 429                                       GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
 430                                       GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
 431                                       GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
 432                                       GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
 433                         interrupt-names = "error",
 434                                         "ch0", "ch1", "ch2", "ch3",
 435                                         "ch4", "ch5", "ch6", "ch7";
 436                         clocks = <&cpg CPG_MOD 217>;
 437                         clock-names = "fck";
 438                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 439                         resets = <&cpg 217>;
 440                         #dma-cells = <1>;
 441                         dma-channels = <8>;
 442                 };
 443
 444                 ipmmu_ds0: mmu@e6740000 {
 445                         compatible = "renesas,ipmmu-r8a77995";
 446                         reg = <0 0xe6740000 0 0x1000>;
 447                         renesas,ipmmu-main = <&ipmmu_mm 0>;
 448                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 449                         #iommu-cells = <1>;
 450                 };
 451
 452                 ipmmu_ds1: mmu@e7740000 {
 453                         compatible = "renesas,ipmmu-r8a77995";
 454                         reg = <0 0xe7740000 0 0x1000>;
 455                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 456                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 457                         #iommu-cells = <1>;
 458                 };
 459
 460                 ipmmu_hc: mmu@e6570000 {
 461                         compatible = "renesas,ipmmu-r8a77995";
 462                         reg = <0 0xe6570000 0 0x1000>;
 463                         renesas,ipmmu-main = <&ipmmu_mm 2>;
 464                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 465                         #iommu-cells = <1>;
 466                 };
 467
 468                 ipmmu_mm: mmu@e67b0000 {
 469                         compatible = "renesas,ipmmu-r8a77995";
 470                         reg = <0 0xe67b0000 0 0x1000>;
 471                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 472                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 473                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 474                         #iommu-cells = <1>;
 475                 };
 476
 477                 ipmmu_mp: mmu@ec670000 {
 478                         compatible = "renesas,ipmmu-r8a77995";
 479                         reg = <0 0xec670000 0 0x1000>;
 480                         renesas,ipmmu-main = <&ipmmu_mm 4>;
 481                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 482                         #iommu-cells = <1>;
 483                 };
 484
 485                 ipmmu_pv0: mmu@fd800000 {
 486                         compatible = "renesas,ipmmu-r8a77995";
 487                         reg = <0 0xfd800000 0 0x1000>;
 488                         renesas,ipmmu-main = <&ipmmu_mm 6>;
 489                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 490                         #iommu-cells = <1>;
 491                 };
 492
 493                 ipmmu_rt: mmu@ffc80000 {
 494                         compatible = "renesas,ipmmu-r8a77995";
 495                         reg = <0 0xffc80000 0 0x1000>;
 496                         renesas,ipmmu-main = <&ipmmu_mm 10>;
 497                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 498                         #iommu-cells = <1>;
 499                 };
 500
 501                 ipmmu_vc0: mmu@fe6b0000 {
 502                         compatible = "renesas,ipmmu-r8a77995";
 503                         reg = <0 0xfe6b0000 0 0x1000>;
 504                         renesas,ipmmu-main = <&ipmmu_mm 12>;
 505                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 506                         #iommu-cells = <1>;
 507                 };
 508
 509                 ipmmu_vi0: mmu@febd0000 {
 510                         compatible = "renesas,ipmmu-r8a77995";
 511                         reg = <0 0xfebd0000 0 0x1000>;
 512                         renesas,ipmmu-main = <&ipmmu_mm 14>;
 513                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 514                         #iommu-cells = <1>;
 515                 };
 516
 517                 ipmmu_vp0: mmu@fe990000 {
 518                         compatible = "renesas,ipmmu-r8a77995";
 519                         reg = <0 0xfe990000 0 0x1000>;
 520                         renesas,ipmmu-main = <&ipmmu_mm 16>;
 521                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 522                         #iommu-cells = <1>;
 523                 };
 524
 525                 avb: ethernet@e6800000 {
 526                         compatible = "renesas,etheravb-r8a77995",
 527                                      "renesas,etheravb-rcar-gen3";
 528                         reg = <0 0xe6800000 0 0x800>;
 529                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 530                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 531                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 532                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 540                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 542                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 544                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 545                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 548                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 551                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 553                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 554                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 555                                           "ch4", "ch5", "ch6", "ch7",
 556                                           "ch8", "ch9", "ch10", "ch11",
 557                                           "ch12", "ch13", "ch14", "ch15",
 558                                           "ch16", "ch17", "ch18", "ch19",
 559                                           "ch20", "ch21", "ch22", "ch23",
 560                                           "ch24";
 561                         clocks = <&cpg CPG_MOD 812>;
 562                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 563                         resets = <&cpg 812>;
 564                         phy-mode = "rgmii";
 565                         iommus = <&ipmmu_ds0 16>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         status = "disabled";
 569                 };
 570
 571                 can0: can@e6c30000 {
 572                         compatible = "renesas,can-r8a77995",
 573                                      "renesas,rcar-gen3-can";
 574                         reg = <0 0xe6c30000 0 0x1000>;
 575                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&cpg CPG_MOD 916>,
 577                                <&cpg CPG_CORE R8A77995_CLK_CANFD>,
 578                                <&can_clk>;
 579                         clock-names = "clkp1", "clkp2", "can_clk";
 580                         assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
 581                         assigned-clock-rates = <40000000>;
 582                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 583                         resets = <&cpg 916>;
 584                         status = "disabled";
 585                 };
 586
 587                 can1: can@e6c38000 {
 588                         compatible = "renesas,can-r8a77995",
 589                                      "renesas,rcar-gen3-can";
 590                         reg = <0 0xe6c38000 0 0x1000>;
 591                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 592                         clocks = <&cpg CPG_MOD 915>,
 593                                <&cpg CPG_CORE R8A77995_CLK_CANFD>,
 594                                <&can_clk>;
 595                         clock-names = "clkp1", "clkp2", "can_clk";
 596                         assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
 597                         assigned-clock-rates = <40000000>;
 598                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 599                         resets = <&cpg 915>;
 600                         status = "disabled";
 601                 };
 602
 603                 pwm0: pwm@e6e30000 {
 604                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 605                         reg = <0 0xe6e30000 0 0x8>;
 606                         #pwm-cells = <2>;
 607                         clocks = <&cpg CPG_MOD 523>;
 608                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 609                         resets = <&cpg 523>;
 610                         status = "disabled";
 611                 };
 612
 613                 pwm1: pwm@e6e31000 {
 614                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 615                         reg = <0 0xe6e31000 0 0x8>;
 616                         #pwm-cells = <2>;
 617                         clocks = <&cpg CPG_MOD 523>;
 618                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 619                         resets = <&cpg 523>;
 620                         status = "disabled";
 621                 };
 622
 623                 pwm2: pwm@e6e32000 {
 624                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 625                         reg = <0 0xe6e32000 0 0x8>;
 626                         #pwm-cells = <2>;
 627                         clocks = <&cpg CPG_MOD 523>;
 628                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 629                         resets = <&cpg 523>;
 630                         status = "disabled";
 631                 };
 632
 633                 pwm3: pwm@e6e33000 {
 634                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
 635                         reg = <0 0xe6e33000 0 0x8>;
 636                         #pwm-cells = <2>;
 637                         clocks = <&cpg CPG_MOD 523>;
 638                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 639                         resets = <&cpg 523>;
 640                         status = "disabled";
 641                 };
 642
 643                 scif0: serial@e6e60000 {
 644                         compatible = "renesas,scif-r8a77995",
 645                                      "renesas,rcar-gen3-scif", "renesas,scif";
 646                         reg = <0 0xe6e60000 0 64>;
 647                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 648                         clocks = <&cpg CPG_MOD 207>,
 649                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 650                                  <&scif_clk>;
 651                         clock-names = "fck", "brg_int", "scif_clk";
 652                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 653                                <&dmac2 0x51>, <&dmac2 0x50>;
 654                         dma-names = "tx", "rx", "tx", "rx";
 655                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 656                         resets = <&cpg 207>;
 657                         status = "disabled";
 658                 };
 659
 660                 scif1: serial@e6e68000 {
 661                         compatible = "renesas,scif-r8a77995",
 662                                      "renesas,rcar-gen3-scif", "renesas,scif";
 663                         reg = <0 0xe6e68000 0 64>;
 664                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&cpg CPG_MOD 206>,
 666                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 667                                  <&scif_clk>;
 668                         clock-names = "fck", "brg_int", "scif_clk";
 669                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 670                                <&dmac2 0x53>, <&dmac2 0x52>;
 671                         dma-names = "tx", "rx", "tx", "rx";
 672                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 673                         resets = <&cpg 206>;
 674                         status = "disabled";
 675                 };
 676
 677                 scif2: serial@e6e88000 {
 678                         compatible = "renesas,scif-r8a77995",
 679                                      "renesas,rcar-gen3-scif", "renesas,scif";
 680                         reg = <0 0xe6e88000 0 64>;
 681                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 682                         clocks = <&cpg CPG_MOD 310>,
 683                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 684                                  <&scif_clk>;
 685                         clock-names = "fck", "brg_int", "scif_clk";
 686                         dmas = <&dmac1 0x13>, <&dmac1 0x12>,
 687                                <&dmac2 0x13>, <&dmac2 0x12>;
 688                         dma-names = "tx", "rx", "tx", "rx";
 689                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 690                         resets = <&cpg 310>;
 691                         status = "disabled";
 692                 };
 693
 694                 scif3: serial@e6c50000 {
 695                         compatible = "renesas,scif-r8a77995",
 696                                      "renesas,rcar-gen3-scif", "renesas,scif";
 697                         reg = <0 0xe6c50000 0 64>;
 698                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 699                         clocks = <&cpg CPG_MOD 204>,
 700                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 701                                  <&scif_clk>;
 702                         clock-names = "fck", "brg_int", "scif_clk";
 703                         dmas = <&dmac0 0x57>, <&dmac0 0x56>;
 704                         dma-names = "tx", "rx";
 705                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 706                         resets = <&cpg 204>;
 707                         status = "disabled";
 708                 };
 709
 710                 scif4: serial@e6c40000 {
 711                         compatible = "renesas,scif-r8a77995",
 712                                      "renesas,rcar-gen3-scif", "renesas,scif";
 713                         reg = <0 0xe6c40000 0 64>;
 714                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 715                         clocks = <&cpg CPG_MOD 203>,
 716                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 717                                  <&scif_clk>;
 718                         clock-names = "fck", "brg_int", "scif_clk";
 719                         dmas = <&dmac0 0x59>, <&dmac0 0x58>;
 720                         dma-names = "tx", "rx";
 721                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 722                         resets = <&cpg 203>;
 723                         status = "disabled";
 724                 };
 725
 726                 scif5: serial@e6f30000 {
 727                         compatible = "renesas,scif-r8a77995",
 728                                      "renesas,rcar-gen3-scif", "renesas,scif";
 729                         reg = <0 0xe6f30000 0 64>;
 730                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 731                         clocks = <&cpg CPG_MOD 202>,
 732                                  <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
 733                                  <&scif_clk>;
 734                         clock-names = "fck", "brg_int", "scif_clk";
 735                         dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
 736                                <&dmac2 0x5b>, <&dmac2 0x5a>;
 737                         dma-names = "tx", "rx", "tx", "rx";
 738                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 739                         resets = <&cpg 202>;
 740                         status = "disabled";
 741                 };
 742
 743                 msiof0: spi@e6e90000 {
 744                         compatible = "renesas,msiof-r8a77995",
 745                                      "renesas,rcar-gen3-msiof";
 746                         reg = <0 0xe6e90000 0 0x64>;
 747                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&cpg CPG_MOD 211>;
 749                         dmas = <&dmac1 0x41>, <&dmac1 0x40>,
 750                                <&dmac2 0x41>, <&dmac2 0x40>;
 751                         dma-names = "tx", "rx", "tx", "rx";
 752                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 753                         resets = <&cpg 211>;
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         status = "disabled";
 757                 };
 758
 759                 msiof1: spi@e6ea0000 {
 760                         compatible = "renesas,msiof-r8a77995",
 761                                      "renesas,rcar-gen3-msiof";
 762                         reg = <0 0xe6ea0000 0 0x64>;
 763                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 764                         clocks = <&cpg CPG_MOD 210>;
 765                         dmas = <&dmac1 0x43>, <&dmac1 0x42>,
 766                                <&dmac2 0x43>, <&dmac2 0x42>;
 767                         dma-names = "tx", "rx", "tx", "rx";
 768                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 769                         resets = <&cpg 210>;
 770                         #address-cells = <1>;
 771                         #size-cells = <0>;
 772                         status = "disabled";
 773                 };
 774
 775                 msiof2: spi@e6c00000 {
 776                         compatible = "renesas,msiof-r8a77995",
 777                                      "renesas,rcar-gen3-msiof";
 778                         reg = <0 0xe6c00000 0 0x64>;
 779                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 780                         clocks = <&cpg CPG_MOD 209>;
 781                         dmas = <&dmac0 0x45>, <&dmac0 0x44>;
 782                         dma-names = "tx", "rx";
 783                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 784                         resets = <&cpg 209>;
 785                         #address-cells = <1>;
 786                         #size-cells = <0>;
 787                         status = "disabled";
 788                 };
 789
 790                 msiof3: spi@e6c10000 {
 791                         compatible = "renesas,msiof-r8a77995",
 792                                      "renesas,rcar-gen3-msiof";
 793                         reg = <0 0xe6c10000 0 0x64>;
 794                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 795                         clocks = <&cpg CPG_MOD 208>;
 796                         dmas = <&dmac0 0x47>, <&dmac0 0x46>;
 797                         dma-names = "tx", "rx";
 798                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 799                         resets = <&cpg 208>;
 800                         #address-cells = <1>;
 801                         #size-cells = <0>;
 802                         status = "disabled";
 803                 };
 804
 805                 vin4: video@e6ef4000 {
 806                         compatible = "renesas,vin-r8a77995";
 807                         reg = <0 0xe6ef4000 0 0x1000>;
 808                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 809                         clocks = <&cpg CPG_MOD 807>;
 810                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 811                         resets = <&cpg 807>;
 812                         renesas,id = <4>;
 813                         status = "disabled";
 814                 };
 815
 816                 ohci0: usb@ee080000 {
 817                         compatible = "generic-ohci";
 818                         reg = <0 0xee080000 0 0x100>;
 819                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 820                         clocks = <&cpg CPG_MOD 703>;
 821                         phys = <&usb2_phy0>;
 822                         phy-names = "usb";
 823                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 824                         resets = <&cpg 703>;
 825                         status = "disabled";
 826                 };
 827
 828                 ehci0: usb@ee080100 {
 829                         compatible = "generic-ehci";
 830                         reg = <0 0xee080100 0 0x100>;
 831                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 832                         clocks = <&cpg CPG_MOD 703>;
 833                         phys = <&usb2_phy0>;
 834                         phy-names = "usb";
 835                         companion = <&ohci0>;
 836                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 837                         resets = <&cpg 703>;
 838                         status = "disabled";
 839                 };
 840
 841                 usb2_phy0: usb-phy@ee080200 {
 842                         compatible = "renesas,usb2-phy-r8a77995",
 843                                      "renesas,rcar-gen3-usb2-phy";
 844                         reg = <0 0xee080200 0 0x700>;
 845                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 846                         clocks = <&cpg CPG_MOD 703>;
 847                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 848                         resets = <&cpg 703>;
 849                         #phy-cells = <0>;
 850                         status = "disabled";
 851                 };
 852
 853                 sdhi2: sd@ee140000 {
 854                         compatible = "renesas,sdhi-r8a77995",
 855                                      "renesas,rcar-gen3-sdhi";
 856                         reg = <0 0xee140000 0 0x2000>;
 857                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 858                         clocks = <&cpg CPG_MOD 312>;
 859                         max-frequency = <200000000>;
 860                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 861                         resets = <&cpg 312>;
 862                         status = "disabled";
 863                 };
 864
 865                 gic: interrupt-controller@f1010000 {
 866                         compatible = "arm,gic-400";
 867                         #interrupt-cells = <3>;
 868                         #address-cells = <0>;
 869                         interrupt-controller;
 870                         reg = <0x0 0xf1010000 0 0x1000>,
 871                               <0x0 0xf1020000 0 0x20000>,
 872                               <0x0 0xf1040000 0 0x20000>,
 873                               <0x0 0xf1060000 0 0x20000>;
 874                         interrupts = <GIC_PPI 9
 875                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 876                         clocks = <&cpg CPG_MOD 408>;
 877                         clock-names = "clk";
 878                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 879                         resets = <&cpg 408>;
 880                 };
 881
 882                 vspbs: vsp@fe960000 {
 883                         compatible = "renesas,vsp2";
 884                         reg = <0 0xfe960000 0 0x8000>;
 885                         interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
 886                         clocks = <&cpg CPG_MOD 627>;
 887                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 888                         resets = <&cpg 627>;
 889                         renesas,fcp = <&fcpvb0>;
 890                 };
 891
 892                 vspd0: vsp@fea20000 {
 893                         compatible = "renesas,vsp2";
 894                         reg = <0 0xfea20000 0 0x5000>;
 895                         interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&cpg CPG_MOD 623>;
 897                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 898                         resets = <&cpg 623>;
 899                         renesas,fcp = <&fcpvd0>;
 900                 };
 901
 902                 vspd1: vsp@fea28000 {
 903                         compatible = "renesas,vsp2";
 904                         reg = <0 0xfea28000 0 0x5000>;
 905                         interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
 906                         clocks = <&cpg CPG_MOD 622>;
 907                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 908                         resets = <&cpg 622>;
 909                         renesas,fcp = <&fcpvd1>;
 910                 };
 911
 912                 fcpvb0: fcp@fe96f000 {
 913                         compatible = "renesas,fcpv";
 914                         reg = <0 0xfe96f000 0 0x200>;
 915                         clocks = <&cpg CPG_MOD 607>;
 916                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 917                         resets = <&cpg 607>;
 918                         iommus = <&ipmmu_vp0 5>;
 919                 };
 920
 921                 fcpvd0: fcp@fea27000 {
 922                         compatible = "renesas,fcpv";
 923                         reg = <0 0xfea27000 0 0x200>;
 924                         clocks = <&cpg CPG_MOD 603>;
 925                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 926                         resets = <&cpg 603>;
 927                         iommus = <&ipmmu_vi0 8>;
 928                 };
 929
 930                 fcpvd1: fcp@fea2f000 {
 931                         compatible = "renesas,fcpv";
 932                         reg = <0 0xfea2f000 0 0x200>;
 933                         clocks = <&cpg CPG_MOD 602>;
 934                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
 935                         resets = <&cpg 602>;
 936                         iommus = <&ipmmu_vi0 9>;
 937                 };
 938
 939                 du: display@feb00000 {
 940                         compatible = "renesas,du-r8a77995";
 941                         reg = <0 0xfeb00000 0 0x80000>;
 942                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 943                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 944                         clocks = <&cpg CPG_MOD 724>,
 945                                  <&cpg CPG_MOD 723>;
 946                         clock-names = "du.0", "du.1";
 947                         vsps = <&vspd0 0 &vspd1 0>;
 948                         status = "disabled";
 949
 950                         ports {
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953
 954                                 port@0 {
 955                                         reg = <0>;
 956                                         du_out_rgb: endpoint {
 957                                         };
 958                                 };
 959
 960                                 port@1 {
 961                                         reg = <1>;
 962                                         du_out_lvds0: endpoint {
 963                                         };
 964                                 };
 965
 966                                 port@2 {
 967                                         reg = <2>;
 968                                         du_out_lvds1: endpoint {
 969                                         };
 970                                 };
 971                         };
 972                 };
 973
 974                 prr: chipid@fff00044 {
 975                         compatible = "renesas,prr";
 976                         reg = <0 0xfff00044 0 4>;
 977                 };
 978         };
 979
 980         thermal-zones {
 981                 cpu_thermal: cpu-thermal {
 982                         polling-delay-passive = <250>;
 983                         polling-delay = <1000>;
 984                         thermal-sensors = <&thermal>;
 985
 986                         trips {
 987                                 cpu-crit {
 988                                         temperature = <120000>;
 989                                         hysteresis = <2000>;
 990                                         type = "critical";
 991                                 };
 992                         };
 993
 994                         cooling-maps {
 995                         };
 996                 };
 997         };
 998
 999         timer {
1000                 compatible = "arm,armv8-timer";
1001                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1002                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1003                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1004                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
1005         };
1006 };