arch/arm/dts/r8a77990.dtsi

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Device Tree Source for the r8a77990 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a77990-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a77990";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 a53_0: cpu@0 {
  22                         compatible = "arm,cortex-a53", "arm,armv8";
  23                         reg = <0>;
  24                         device_type = "cpu";
  25                         power-domains = <&sysc 5>;
  26                         next-level-cache = <&L2_CA53>;
  27                         enable-method = "psci";
  28                 };
  29
  30                 a53_1: cpu@1 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         reg = <1>;
  33                         device_type = "cpu";
  34                         power-domains = <&sysc 6>;
  35                         next-level-cache = <&L2_CA53>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 L2_CA53: cache-controller-0 {
  40                         compatible = "cache";
  41                         power-domains = <&sysc 21>;
  42                         cache-unified;
  43                         cache-level = <2>;
  44                 };
  45         };
  46
  47         extal_clk: extal {
  48                 compatible = "fixed-clock";
  49                 #clock-cells = <0>;
  50                 /* This value must be overridden by the board */
  51                 clock-frequency = <0>;
  52         };
  53
  54         pmu_a53 {
  55                 compatible = "arm,cortex-a53-pmu";
  56                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  57                                       <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  58                 interrupt-affinity = <&a53_0>, <&a53_1>;
  59         };
  60
  61         psci {
  62                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  63                 method = "smc";
  64         };
  65
  66         soc: soc {
  67                 compatible = "simple-bus";
  68                 interrupt-parent = <&gic>;
  69                 #address-cells = <2>;
  70                 #size-cells = <2>;
  71                 ranges;
  72
  73                 rwdt: watchdog@e6020000 {
  74                         compatible = "renesas,r8a77990-wdt",
  75                                      "renesas,rcar-gen3-wdt";
  76                         reg = <0 0xe6020000 0 0x0c>;
  77                         clocks = <&cpg CPG_MOD 402>;
  78                         power-domains = <&sysc 32>;
  79                         resets = <&cpg 402>;
  80                         status = "disabled";
  81                 };
  82
  83                 gpio0: gpio@e6050000 {
  84                         compatible = "renesas,gpio-r8a77990",
  85                                      "renesas,rcar-gen3-gpio";
  86                         reg = <0 0xe6050000 0 0x50>;
  87                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  88                         #gpio-cells = <2>;
  89                         gpio-controller;
  90                         gpio-ranges = <&pfc 0 0 18>;
  91                         #interrupt-cells = <2>;
  92                         interrupt-controller;
  93                         clocks = <&cpg CPG_MOD 912>;
  94                         power-domains = <&sysc 32>;
  95                         resets = <&cpg 912>;
  96                 };
  97
  98                 gpio1: gpio@e6051000 {
  99                         compatible = "renesas,gpio-r8a77990",
 100                                      "renesas,rcar-gen3-gpio";
 101                         reg = <0 0xe6051000 0 0x50>;
 102                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 103                         #gpio-cells = <2>;
 104                         gpio-controller;
 105                         gpio-ranges = <&pfc 0 32 23>;
 106                         #interrupt-cells = <2>;
 107                         interrupt-controller;
 108                         clocks = <&cpg CPG_MOD 911>;
 109                         power-domains = <&sysc 32>;
 110                         resets = <&cpg 911>;
 111                 };
 112
 113                 gpio2: gpio@e6052000 {
 114                         compatible = "renesas,gpio-r8a77990",
 115                                      "renesas,rcar-gen3-gpio";
 116                         reg = <0 0xe6052000 0 0x50>;
 117                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 118                         #gpio-cells = <2>;
 119                         gpio-controller;
 120                         gpio-ranges = <&pfc 0 64 26>;
 121                         #interrupt-cells = <2>;
 122                         interrupt-controller;
 123                         clocks = <&cpg CPG_MOD 910>;
 124                         power-domains = <&sysc 32>;
 125                         resets = <&cpg 910>;
 126                 };
 127
 128                 gpio3: gpio@e6053000 {
 129                         compatible = "renesas,gpio-r8a77990",
 130                                      "renesas,rcar-gen3-gpio";
 131                         reg = <0 0xe6053000 0 0x50>;
 132                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 133                         #gpio-cells = <2>;
 134                         gpio-controller;
 135                         gpio-ranges = <&pfc 0 96 16>;
 136                         #interrupt-cells = <2>;
 137                         interrupt-controller;
 138                         clocks = <&cpg CPG_MOD 909>;
 139                         power-domains = <&sysc 32>;
 140                         resets = <&cpg 909>;
 141                 };
 142
 143                 gpio4: gpio@e6054000 {
 144                         compatible = "renesas,gpio-r8a77990",
 145                                      "renesas,rcar-gen3-gpio";
 146                         reg = <0 0xe6054000 0 0x50>;
 147                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 148                         #gpio-cells = <2>;
 149                         gpio-controller;
 150                         gpio-ranges = <&pfc 0 128 11>;
 151                         #interrupt-cells = <2>;
 152                         interrupt-controller;
 153                         clocks = <&cpg CPG_MOD 908>;
 154                         power-domains = <&sysc 32>;
 155                         resets = <&cpg 908>;
 156                 };
 157
 158                 gpio5: gpio@e6055000 {
 159                         compatible = "renesas,gpio-r8a77990",
 160                                      "renesas,rcar-gen3-gpio";
 161                         reg = <0 0xe6055000 0 0x50>;
 162                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 163                         #gpio-cells = <2>;
 164                         gpio-controller;
 165                         gpio-ranges = <&pfc 0 160 20>;
 166                         #interrupt-cells = <2>;
 167                         interrupt-controller;
 168                         clocks = <&cpg CPG_MOD 907>;
 169                         power-domains = <&sysc 32>;
 170                         resets = <&cpg 907>;
 171                 };
 172
 173                 gpio6: gpio@e6055400 {
 174                         compatible = "renesas,gpio-r8a77990",
 175                                      "renesas,rcar-gen3-gpio";
 176                         reg = <0 0xe6055400 0 0x50>;
 177                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 178                         #gpio-cells = <2>;
 179                         gpio-controller;
 180                         gpio-ranges = <&pfc 0 192 18>;
 181                         #interrupt-cells = <2>;
 182                         interrupt-controller;
 183                         clocks = <&cpg CPG_MOD 906>;
 184                         power-domains = <&sysc 32>;
 185                         resets = <&cpg 906>;
 186                 };
 187
 188                 pfc: pin-controller@e6060000 {
 189                         compatible = "renesas,pfc-r8a77990";
 190                         reg = <0 0xe6060000 0 0x508>;
 191                 };
 192
 193                 cpg: clock-controller@e6150000 {
 194                         compatible = "renesas,r8a77990-cpg-mssr";
 195                         reg = <0 0xe6150000 0 0x1000>;
 196                         clocks = <&extal_clk>;
 197                         clock-names = "extal";
 198                         #clock-cells = <2>;
 199                         #power-domain-cells = <0>;
 200                         #reset-cells = <1>;
 201                 };
 202
 203                 rst: reset-controller@e6160000 {
 204                         compatible = "renesas,r8a77990-rst";
 205                         reg = <0 0xe6160000 0 0x0200>;
 206                 };
 207
 208                 sysc: system-controller@e6180000 {
 209                         compatible = "renesas,r8a77990-sysc";
 210                         reg = <0 0xe6180000 0 0x0400>;
 211                         #power-domain-cells = <1>;
 212                 };
 213
 214                 ipmmu_ds0: mmu@e6740000 {
 215                         compatible = "renesas,ipmmu-r8a77990";
 216                         reg = <0 0xe6740000 0 0x1000>;
 217                         renesas,ipmmu-main = <&ipmmu_mm 0>;
 218                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 219                         #iommu-cells = <1>;
 220                 };
 221
 222                 ipmmu_ds1: mmu@e7740000 {
 223                         compatible = "renesas,ipmmu-r8a77990";
 224                         reg = <0 0xe7740000 0 0x1000>;
 225                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 226                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 227                         #iommu-cells = <1>;
 228                 };
 229
 230                 ipmmu_hc: mmu@e6570000 {
 231                         compatible = "renesas,ipmmu-r8a77990";
 232                         reg = <0 0xe6570000 0 0x1000>;
 233                         renesas,ipmmu-main = <&ipmmu_mm 2>;
 234                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 235                         #iommu-cells = <1>;
 236                 };
 237
 238                 ipmmu_mm: mmu@e67b0000 {
 239                         compatible = "renesas,ipmmu-r8a77990";
 240                         reg = <0 0xe67b0000 0 0x1000>;
 241                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 243                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 244                         #iommu-cells = <1>;
 245                 };
 246
 247                 ipmmu_mp: mmu@ec670000 {
 248                         compatible = "renesas,ipmmu-r8a77990";
 249                         reg = <0 0xec670000 0 0x1000>;
 250                         renesas,ipmmu-main = <&ipmmu_mm 4>;
 251                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 252                         #iommu-cells = <1>;
 253                 };
 254
 255                 ipmmu_pv0: mmu@fd800000 {
 256                         compatible = "renesas,ipmmu-r8a77990";
 257                         reg = <0 0xfd800000 0 0x1000>;
 258                         renesas,ipmmu-main = <&ipmmu_mm 6>;
 259                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 260                         #iommu-cells = <1>;
 261                 };
 262
 263                 ipmmu_rt: mmu@ffc80000 {
 264                         compatible = "renesas,ipmmu-r8a77990";
 265                         reg = <0 0xffc80000 0 0x1000>;
 266                         renesas,ipmmu-main = <&ipmmu_mm 10>;
 267                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 268                         #iommu-cells = <1>;
 269                 };
 270
 271                 ipmmu_vc0: mmu@fe6b0000 {
 272                         compatible = "renesas,ipmmu-r8a77990";
 273                         reg = <0 0xfe6b0000 0 0x1000>;
 274                         renesas,ipmmu-main = <&ipmmu_mm 12>;
 275                         power-domains = <&sysc R8A77990_PD_A3VC>;
 276                         #iommu-cells = <1>;
 277                 };
 278
 279                 ipmmu_vi0: mmu@febd0000 {
 280                         compatible = "renesas,ipmmu-r8a77990";
 281                         reg = <0 0xfebd0000 0 0x1000>;
 282                         renesas,ipmmu-main = <&ipmmu_mm 14>;
 283                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 284                         #iommu-cells = <1>;
 285                 };
 286
 287                 ipmmu_vp0: mmu@fe990000 {
 288                         compatible = "renesas,ipmmu-r8a77990";
 289                         reg = <0 0xfe990000 0 0x1000>;
 290                         renesas,ipmmu-main = <&ipmmu_mm 16>;
 291                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 292                         #iommu-cells = <1>;
 293                 };
 294
 295                 avb: ethernet@e6800000 {
 296                         compatible = "renesas,etheravb-r8a77990",
 297                                      "renesas,etheravb-rcar-gen3";
 298                         reg = <0 0xe6800000 0 0x800>;
 299                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 302                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 306                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 312                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 313                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 314                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 315                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 316                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 317                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 318                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 319                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 320                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 321                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 322                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 324                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 325                                           "ch4", "ch5", "ch6", "ch7",
 326                                           "ch8", "ch9", "ch10", "ch11",
 327                                           "ch12", "ch13", "ch14", "ch15",
 328                                           "ch16", "ch17", "ch18", "ch19",
 329                                           "ch20", "ch21", "ch22", "ch23",
 330                                           "ch24";
 331                         clocks = <&cpg CPG_MOD 812>;
 332                         power-domains = <&sysc 32>;
 333                         resets = <&cpg 812>;
 334                         phy-mode = "rgmii";
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         status = "disabled";
 338                 };
 339
 340                 scif2: serial@e6e88000 {
 341                         compatible = "renesas,scif-r8a77990",
 342                                      "renesas,rcar-gen3-scif", "renesas,scif";
 343                         reg = <0 0xe6e88000 0 64>;
 344                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 345                         clocks = <&cpg CPG_MOD 310>;
 346                         clock-names = "fck";
 347                         power-domains = <&sysc 32>;
 348                         resets = <&cpg 310>;
 349                         status = "disabled";
 350                 };
 351
 352                 xhci0: usb@ee000000 {
 353                         compatible = "renesas,xhci-r8a77990",
 354                                      "renesas,rcar-gen3-xhci";
 355                         reg = <0 0xee000000 0 0xc00>;
 356                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&cpg CPG_MOD 328>;
 358                         power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
 359                         resets = <&cpg 328>;
 360                         status = "disabled";
 361                 };
 362
 363                 ohci0: usb@ee080000 {
 364                         compatible = "generic-ohci";
 365                         reg = <0 0xee080000 0 0x100>;
 366                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&cpg CPG_MOD 703>;
 368                         phys = <&usb2_phy0>;
 369                         phy-names = "usb";
 370                         power-domains = <&sysc 32>;
 371                         resets = <&cpg 703>;
 372                         status = "disabled";
 373                 };
 374
 375                 ehci0: usb@ee080100 {
 376                         compatible = "generic-ehci";
 377                         reg = <0 0xee080100 0 0x100>;
 378                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 379                         clocks = <&cpg CPG_MOD 703>;
 380                         phys = <&usb2_phy0>;
 381                         phy-names = "usb";
 382                         companion = <&ohci0>;
 383                         power-domains = <&sysc 32>;
 384                         resets = <&cpg 703>;
 385                         status = "disabled";
 386                 };
 387
 388                 usb2_phy0: usb-phy@ee080200 {
 389                         compatible = "renesas,usb2-phy-r8a77990",
 390                                      "renesas,rcar-gen3-usb2-phy";
 391                         reg = <0 0xee080200 0 0x700>;
 392                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 393                         clocks = <&cpg CPG_MOD 703>;
 394                         power-domains = <&sysc 32>;
 395                         resets = <&cpg 703>;
 396                         #phy-cells = <0>;
 397                         status = "disabled";
 398                 };
 399
 400                 gic: interrupt-controller@f1010000 {
 401                         compatible = "arm,gic-400";
 402                         #interrupt-cells = <3>;
 403                         #address-cells = <0>;
 404                         interrupt-controller;
 405                         reg = <0x0 0xf1010000 0 0x1000>,
 406                               <0x0 0xf1020000 0 0x20000>,
 407                               <0x0 0xf1040000 0 0x20000>,
 408                               <0x0 0xf1060000 0 0x20000>;
 409                         interrupts = <GIC_PPI 9
 410                                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 411                         clocks = <&cpg CPG_MOD 408>;
 412                         clock-names = "clk";
 413                         power-domains = <&sysc 32>;
 414                         resets = <&cpg 408>;
 415                 };
 416
 417                 prr: chipid@fff00044 {
 418                         compatible = "renesas,prr";
 419                         reg = <0 0xfff00044 0 4>;
 420                 };
 421         };
 422
 423         timer {
 424                 compatible = "arm,armv8-timer";
 425                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 426                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 427                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 428                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 429         };
 430 };