arch/arm/dts/r8a77970.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77970 SoC
   4  *
   5  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   6  * Copyright (C) 2017 Cogent Embedded, Inc.
   7  */
   8
   9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/power/r8a77970-sysc.h>
  13
  14 / {
  15         compatible = "renesas,r8a77970";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 i2c4 = &i2c4;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 a53_0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53", "arm,armv8";
  34                         reg = <0>;
  35                         clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
  36                         power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
  37                         next-level-cache = <&L2_CA53>;
  38                         enable-method = "psci";
  39                 };
  40
  41                 L2_CA53: cache-controller {
  42                         compatible = "cache";
  43                         power-domains = <&sysc R8A77970_PD_CA53_SCU>;
  44                         cache-unified;
  45                         cache-level = <2>;
  46                 };
  47         };
  48
  49         extal_clk: extal {
  50                 compatible = "fixed-clock";
  51                 #clock-cells = <0>;
  52                 /* This value must be overridden by the board */
  53                 clock-frequency = <0>;
  54         };
  55
  56         extalr_clk: extalr {
  57                 compatible = "fixed-clock";
  58                 #clock-cells = <0>;
  59                 /* This value must be overridden by the board */
  60                 clock-frequency = <0>;
  61         };
  62
  63         psci {
  64                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  65                 method = "smc";
  66         };
  67
  68         /* External SCIF clock - to be overridden by boards that provide it */
  69         scif_clk: scif {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <0>;
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 interrupt-parent = <&gic>;
  78
  79                 #address-cells = <2>;
  80                 #size-cells = <2>;
  81                 ranges;
  82
  83                 gic: interrupt-controller@f1010000 {
  84                         compatible = "arm,gic-400";
  85                         #interrupt-cells = <3>;
  86                         #address-cells = <0>;
  87                         interrupt-controller;
  88                         reg = <0 0xf1010000 0 0x1000>,
  89                               <0 0xf1020000 0 0x20000>,
  90                               <0 0xf1040000 0 0x20000>,
  91                               <0 0xf1060000 0 0x20000>;
  92                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
  93                                       IRQ_TYPE_LEVEL_HIGH)>;
  94                         clocks = <&cpg CPG_MOD 408>;
  95                         clock-names = "clk";
  96                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
  97                         resets = <&cpg 408>;
  98                 };
  99
 100                 rwdt: watchdog@e6020000 {
 101                         compatible = "renesas,r8a77970-wdt",
 102                                      "renesas,rcar-gen3-wdt";
 103                         reg = <0 0xe6020000 0 0x0c>;
 104                         clocks = <&cpg CPG_MOD 402>;
 105                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 106                         resets = <&cpg 402>;
 107                         status = "disabled";
 108                 };
 109
 110                 cpg: clock-controller@e6150000 {
 111                         compatible = "renesas,r8a77970-cpg-mssr";
 112                         reg = <0 0xe6150000 0 0x1000>;
 113                         clocks = <&extal_clk>, <&extalr_clk>;
 114                         clock-names = "extal", "extalr";
 115                         #clock-cells = <2>;
 116                         #power-domain-cells = <0>;
 117                         #reset-cells = <1>;
 118                 };
 119
 120                 rst: reset-controller@e6160000 {
 121                         compatible = "renesas,r8a77970-rst";
 122                         reg = <0 0xe6160000 0 0x200>;
 123                 };
 124
 125                 sysc: system-controller@e6180000 {
 126                         compatible = "renesas,r8a77970-sysc";
 127                         reg = <0 0xe6180000 0 0x440>;
 128                         #power-domain-cells = <1>;
 129                 };
 130
 131                 ipmmu_vi0: mmu@febd0000 {
 132                         compatible = "renesas,ipmmu-r8a77970";
 133                         reg = <0 0xfebd0000 0 0x1000>;
 134                         renesas,ipmmu-main = <&ipmmu_mm 9>;
 135                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 136                         #iommu-cells = <1>;
 137                         status = "disabled";
 138                 };
 139
 140                 ipmmu_ir: mmu@ff8b0000 {
 141                         compatible = "renesas,ipmmu-r8a77970";
 142                         reg = <0 0xff8b0000 0 0x1000>;
 143                         renesas,ipmmu-main = <&ipmmu_mm 3>;
 144                         power-domains = <&sysc R8A77970_PD_A3IR>;
 145                         #iommu-cells = <1>;
 146                         status = "disabled";
 147                 };
 148
 149                 ipmmu_rt: mmu@ffc80000 {
 150                         compatible = "renesas,ipmmu-r8a77970";
 151                         reg = <0 0xffc80000 0 0x1000>;
 152                         renesas,ipmmu-main = <&ipmmu_mm 7>;
 153                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 154                         #iommu-cells = <1>;
 155                 };
 156
 157                 ipmmu_ds1: mmu@e7740000 {
 158                         compatible = "renesas,ipmmu-r8a77970";
 159                         reg = <0 0xe7740000 0 0x1000>;
 160                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 161                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 162                         #iommu-cells = <1>;
 163                 };
 164
 165                 ipmmu_mm: mmu@e67b0000 {
 166                         compatible = "renesas,ipmmu-r8a77970";
 167                         reg = <0 0xe67b0000 0 0x1000>;
 168                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 169                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 170                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 171                         #iommu-cells = <1>;
 172                 };
 173
 174                 pfc: pin-controller@e6060000 {
 175                         compatible = "renesas,pfc-r8a77970";
 176                         reg = <0 0xe6060000 0 0x504>;
 177                 };
 178
 179                 gpio0: gpio@e6050000 {
 180                         compatible = "renesas,gpio-r8a77970",
 181                                      "renesas,rcar-gen3-gpio";
 182                         reg = <0 0xe6050000 0 0x50>;
 183                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 184                         #gpio-cells = <2>;
 185                         gpio-controller;
 186                         gpio-ranges = <&pfc 0 0 22>;
 187                         #interrupt-cells = <2>;
 188                         interrupt-controller;
 189                         clocks = <&cpg CPG_MOD 912>;
 190                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 191                         resets = <&cpg 912>;
 192                 };
 193
 194                 gpio1: gpio@e6051000 {
 195                         compatible = "renesas,gpio-r8a77970",
 196                                      "renesas,rcar-gen3-gpio";
 197                         reg = <0 0xe6051000 0 0x50>;
 198                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 199                         #gpio-cells = <2>;
 200                         gpio-controller;
 201                         gpio-ranges = <&pfc 0 32 28>;
 202                         #interrupt-cells = <2>;
 203                         interrupt-controller;
 204                         clocks = <&cpg CPG_MOD 911>;
 205                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 206                         resets = <&cpg 911>;
 207                 };
 208
 209                 gpio2: gpio@e6052000 {
 210                         compatible = "renesas,gpio-r8a77970",
 211                                      "renesas,rcar-gen3-gpio";
 212                         reg = <0 0xe6052000 0 0x50>;
 213                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 214                         #gpio-cells = <2>;
 215                         gpio-controller;
 216                         gpio-ranges = <&pfc 0 64 17>;
 217                         #interrupt-cells = <2>;
 218                         interrupt-controller;
 219                         clocks = <&cpg CPG_MOD 910>;
 220                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 221                         resets = <&cpg 910>;
 222                 };
 223
 224                 gpio3: gpio@e6053000 {
 225                         compatible = "renesas,gpio-r8a77970",
 226                                      "renesas,rcar-gen3-gpio";
 227                         reg = <0 0xe6053000 0 0x50>;
 228                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 229                         #gpio-cells = <2>;
 230                         gpio-controller;
 231                         gpio-ranges = <&pfc 0 96 17>;
 232                         #interrupt-cells = <2>;
 233                         interrupt-controller;
 234                         clocks = <&cpg CPG_MOD 909>;
 235                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 236                         resets = <&cpg 909>;
 237                 };
 238
 239                 gpio4: gpio@e6054000 {
 240                         compatible = "renesas,gpio-r8a77970",
 241                                      "renesas,rcar-gen3-gpio";
 242                         reg = <0 0xe6054000 0 0x50>;
 243                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 244                         #gpio-cells = <2>;
 245                         gpio-controller;
 246                         gpio-ranges = <&pfc 0 128 6>;
 247                         #interrupt-cells = <2>;
 248                         interrupt-controller;
 249                         clocks = <&cpg CPG_MOD 908>;
 250                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 251                         resets = <&cpg 908>;
 252                 };
 253
 254                 gpio5: gpio@e6055000 {
 255                         compatible = "renesas,gpio-r8a77970",
 256                                      "renesas,rcar-gen3-gpio";
 257                         reg = <0 0xe6055000 0 0x50>;
 258                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 259                         #gpio-cells = <2>;
 260                         gpio-controller;
 261                         gpio-ranges = <&pfc 0 160 15>;
 262                         #interrupt-cells = <2>;
 263                         interrupt-controller;
 264                         clocks = <&cpg CPG_MOD 907>;
 265                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 266                         resets = <&cpg 907>;
 267                 };
 268
 269                 intc_ex: interrupt-controller@e61c0000 {
 270                         compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
 271                         #interrupt-cells = <2>;
 272                         interrupt-controller;
 273                         reg = <0 0xe61c0000 0 0x200>;
 274                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 275                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 276                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 277                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 278                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 279                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&cpg CPG_MOD 407>;
 281                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 282                         resets = <&cpg 407>;
 283                 };
 284
 285                 prr: chipid@fff00044 {
 286                         compatible = "renesas,prr";
 287                         reg = <0 0xfff00044 0 4>;
 288                 };
 289
 290                 dmac1: dma-controller@e7300000 {
 291                         compatible = "renesas,dmac-r8a77970",
 292                                      "renesas,rcar-dmac";
 293                         reg = <0 0xe7300000 0 0x10000>;
 294                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 295                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 296                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 297                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 298                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 299                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 300                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 301                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 302                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 303                         interrupt-names = "error",
 304                                           "ch0", "ch1", "ch2", "ch3",
 305                                           "ch4", "ch5", "ch6", "ch7";
 306                         clocks = <&cpg CPG_MOD 218>;
 307                         clock-names = "fck";
 308                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 309                         resets = <&cpg 218>;
 310                         #dma-cells = <1>;
 311                         dma-channels = <8>;
 312                         iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
 313                                <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
 314                                <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
 315                                <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
 316                 };
 317
 318                 dmac2: dma-controller@e7310000 {
 319                         compatible = "renesas,dmac-r8a77970",
 320                                      "renesas,rcar-dmac";
 321                         reg = <0 0xe7310000 0 0x10000>;
 322                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 323                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 324                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 325                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 326                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 327                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 328                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 329                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 330                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 331                         interrupt-names = "error",
 332                                           "ch0", "ch1", "ch2", "ch3",
 333                                           "ch4", "ch5", "ch6", "ch7";
 334                         clocks = <&cpg CPG_MOD 217>;
 335                         clock-names = "fck";
 336                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 337                         resets = <&cpg 217>;
 338                         #dma-cells = <1>;
 339                         dma-channels = <8>;
 340                         iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
 341                                <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
 342                                <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
 343                                <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
 344                 };
 345
 346                 i2c0: i2c@e6500000 {
 347                         compatible = "renesas,i2c-r8a77970",
 348                                      "renesas,rcar-gen3-i2c";
 349                         reg = <0 0xe6500000 0 0x40>;
 350                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 351                         clocks = <&cpg CPG_MOD 931>;
 352                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 353                         resets = <&cpg 931>;
 354                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 355                                <&dmac2 0x91>, <&dmac2 0x90>;
 356                         dma-names = "tx", "rx", "tx", "rx";
 357                         i2c-scl-internal-delay-ns = <6>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         status = "disabled";
 361                 };
 362
 363                 i2c1: i2c@e6508000 {
 364                         compatible = "renesas,i2c-r8a77970",
 365                                      "renesas,rcar-gen3-i2c";
 366                         reg = <0 0xe6508000 0 0x40>;
 367                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&cpg CPG_MOD 930>;
 369                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 370                         resets = <&cpg 930>;
 371                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 372                                <&dmac2 0x93>, <&dmac2 0x92>;
 373                         dma-names = "tx", "rx", "tx", "rx";
 374                         i2c-scl-internal-delay-ns = <6>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         status = "disabled";
 378                 };
 379
 380                 i2c2: i2c@e6510000 {
 381                         compatible = "renesas,i2c-r8a77970",
 382                                      "renesas,rcar-gen3-i2c";
 383                         reg = <0 0xe6510000 0 0x40>;
 384                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 385                         clocks = <&cpg CPG_MOD 929>;
 386                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 387                         resets = <&cpg 929>;
 388                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 389                                <&dmac2 0x95>, <&dmac2 0x94>;
 390                         dma-names = "tx", "rx", "tx", "rx";
 391                         i2c-scl-internal-delay-ns = <6>;
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         status = "disabled";
 395                 };
 396
 397                 i2c3: i2c@e66d0000 {
 398                         compatible = "renesas,i2c-r8a77970",
 399                                      "renesas,rcar-gen3-i2c";
 400                         reg = <0 0xe66d0000 0 0x40>;
 401                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&cpg CPG_MOD 928>;
 403                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 404                         resets = <&cpg 928>;
 405                         dmas = <&dmac1 0x97>, <&dmac1 0x96>,
 406                                <&dmac2 0x97>, <&dmac2 0x96>;
 407                         dma-names = "tx", "rx", "tx", "rx";
 408                         i2c-scl-internal-delay-ns = <6>;
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         status = "disabled";
 412                 };
 413
 414                 i2c4: i2c@e66d8000 {
 415                         compatible = "renesas,i2c-r8a77970",
 416                                      "renesas,rcar-gen3-i2c";
 417                         reg = <0 0xe66d8000 0 0x40>;
 418                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 419                         clocks = <&cpg CPG_MOD 927>;
 420                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 421                         resets = <&cpg 927>;
 422                         dmas = <&dmac1 0x99>, <&dmac1 0x98>,
 423                                <&dmac2 0x99>, <&dmac2 0x98>;
 424                         dma-names = "tx", "rx", "tx", "rx";
 425                         i2c-scl-internal-delay-ns = <6>;
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         status = "disabled";
 429                 };
 430
 431                 hscif0: serial@e6540000 {
 432                         compatible = "renesas,hscif-r8a77970",
 433                                      "renesas,rcar-gen3-hscif",
 434                                      "renesas,hscif";
 435                         reg = <0 0xe6540000 0 96>;
 436                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&cpg CPG_MOD 520>,
 438                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 439                                  <&scif_clk>;
 440                         clock-names = "fck", "brg_int", "scif_clk";
 441                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 442                                <&dmac2 0x31>, <&dmac2 0x30>;
 443                         dma-names = "tx", "rx", "tx", "rx";
 444                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 445                         resets = <&cpg 520>;
 446                         status = "disabled";
 447                 };
 448
 449                 hscif1: serial@e6550000 {
 450                         compatible = "renesas,hscif-r8a77970",
 451                                      "renesas,rcar-gen3-hscif",
 452                                      "renesas,hscif";
 453                         reg = <0 0xe6550000 0 96>;
 454                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&cpg CPG_MOD 519>,
 456                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 457                                  <&scif_clk>;
 458                         clock-names = "fck", "brg_int", "scif_clk";
 459                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 460                                <&dmac2 0x33>, <&dmac2 0x32>;
 461                         dma-names = "tx", "rx", "tx", "rx";
 462                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 463                         resets = <&cpg 519>;
 464                         status = "disabled";
 465                 };
 466
 467                 hscif2: serial@e6560000 {
 468                         compatible = "renesas,hscif-r8a77970",
 469                                      "renesas,rcar-gen3-hscif",
 470                                      "renesas,hscif";
 471                         reg = <0 0xe6560000 0 96>;
 472                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&cpg CPG_MOD 518>,
 474                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 475                                  <&scif_clk>;
 476                         clock-names = "fck", "brg_int", "scif_clk";
 477                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 478                                <&dmac2 0x35>, <&dmac2 0x34>;
 479                         dma-names = "tx", "rx", "tx", "rx";
 480                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 481                         resets = <&cpg 518>;
 482                         status = "disabled";
 483                 };
 484
 485                 hscif3: serial@e66a0000 {
 486                         compatible = "renesas,hscif-r8a77970",
 487                                      "renesas,rcar-gen3-hscif", "renesas,hscif";
 488                         reg = <0 0xe66a0000 0 96>;
 489                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&cpg CPG_MOD 517>,
 491                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 492                                  <&scif_clk>;
 493                         clock-names = "fck", "brg_int", "scif_clk";
 494                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 495                                <&dmac2 0x37>, <&dmac2 0x36>;
 496                         dma-names = "tx", "rx", "tx", "rx";
 497                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 498                         resets = <&cpg 517>;
 499                         status = "disabled";
 500                 };
 501
 502                 scif0: serial@e6e60000 {
 503                         compatible = "renesas,scif-r8a77970",
 504                                      "renesas,rcar-gen3-scif",
 505                                      "renesas,scif";
 506                         reg = <0 0xe6e60000 0 64>;
 507                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&cpg CPG_MOD 207>,
 509                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 510                                  <&scif_clk>;
 511                         clock-names = "fck", "brg_int", "scif_clk";
 512                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 513                                <&dmac2 0x51>, <&dmac2 0x50>;
 514                         dma-names = "tx", "rx", "tx", "rx";
 515                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 516                         resets = <&cpg 207>;
 517                         status = "disabled";
 518                 };
 519
 520                 scif1: serial@e6e68000 {
 521                         compatible = "renesas,scif-r8a77970",
 522                                      "renesas,rcar-gen3-scif",
 523                                      "renesas,scif";
 524                         reg = <0 0xe6e68000 0 64>;
 525                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&cpg CPG_MOD 206>,
 527                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 528                                  <&scif_clk>;
 529                         clock-names = "fck", "brg_int", "scif_clk";
 530                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 531                                <&dmac2 0x53>, <&dmac2 0x52>;
 532                         dma-names = "tx", "rx", "tx", "rx";
 533                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 534                         resets = <&cpg 206>;
 535                         status = "disabled";
 536                 };
 537
 538                 scif3: serial@e6c50000 {
 539                         compatible = "renesas,scif-r8a77970",
 540                                      "renesas,rcar-gen3-scif",
 541                                      "renesas,scif";
 542                         reg = <0 0xe6c50000 0 64>;
 543                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&cpg CPG_MOD 204>,
 545                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 546                                  <&scif_clk>;
 547                         clock-names = "fck", "brg_int", "scif_clk";
 548                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 549                                <&dmac2 0x57>, <&dmac2 0x56>;
 550                         dma-names = "tx", "rx", "tx", "rx";
 551                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 552                         resets = <&cpg 204>;
 553                         status = "disabled";
 554                 };
 555
 556                 scif4: serial@e6c40000 {
 557                         compatible = "renesas,scif-r8a77970",
 558                                      "renesas,rcar-gen3-scif", "renesas,scif";
 559                         reg = <0 0xe6c40000 0 64>;
 560                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&cpg CPG_MOD 203>,
 562                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 563                                  <&scif_clk>;
 564                         clock-names = "fck", "brg_int", "scif_clk";
 565                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 566                                <&dmac2 0x59>, <&dmac2 0x58>;
 567                         dma-names = "tx", "rx", "tx", "rx";
 568                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 569                         resets = <&cpg 203>;
 570                         status = "disabled";
 571                 };
 572
 573                 avb: ethernet@e6800000 {
 574                         compatible = "renesas,etheravb-r8a77970",
 575                                      "renesas,etheravb-rcar-gen3";
 576                         reg = <0 0xe6800000 0 0x800>;
 577                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 578                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 579                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 581                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 595                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 600                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 602                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 603                                           "ch4", "ch5", "ch6", "ch7",
 604                                           "ch8", "ch9", "ch10", "ch11",
 605                                           "ch12", "ch13", "ch14", "ch15",
 606                                           "ch16", "ch17", "ch18", "ch19",
 607                                           "ch20", "ch21", "ch22", "ch23",
 608                                           "ch24";
 609                         clocks = <&cpg CPG_MOD 812>;
 610                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 611                         resets = <&cpg 812>;
 612                         phy-mode = "rgmii";
 613                         iommus = <&ipmmu_rt 3>;
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                 };
 617
 618                 rpc: rpc@0xee200000 {
 619                         compatible = "renesas,rpc-r8a77970", "renesas,rpc";
 620                         reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 621                         clocks = <&cpg CPG_MOD 917>;
 622                         bank-width = <2>;
 623                         status = "disabled";
 624                 };
 625         };
 626
 627         timer {
 628                 compatible = "arm,armv8-timer";
 629                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 630                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 631                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 632                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 633         };
 634 };