arch/arm/dts/r8a77970.dtsi

   1 /*
   2  * Device Tree Source for the r8a77970 SoC
   3  *
   4  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Cogent Embedded, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  15
  16 / {
  17         compatible = "renesas,r8a77970";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         psci {
  22                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  23                 method = "smc";
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 a53_0: cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a53", "arm,armv8";
  33                         reg = <0>;
  34                         clocks = <&cpg CPG_CORE 0>;
  35                         power-domains = <&sysc 5>;
  36                         next-level-cache = <&L2_CA53>;
  37                         enable-method = "psci";
  38                 };
  39
  40                 L2_CA53: cache-controller {
  41                         compatible = "cache";
  42                         power-domains = <&sysc 21>;
  43                         cache-unified;
  44                         cache-level = <2>;
  45                 };
  46         };
  47
  48         extal_clk: extal {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 /* This value must be overridden by the board */
  52                 clock-frequency = <0>;
  53                 u-boot,dm-pre-reloc;
  54         };
  55
  56         extalr_clk: extalr {
  57                 compatible = "fixed-clock";
  58                 #clock-cells = <0>;
  59                 /* This value must be overridden by the board */
  60                 clock-frequency = <0>;
  61                 u-boot,dm-pre-reloc;
  62         };
  63
  64         /* External SCIF clock - to be overridden by boards that provide it */
  65         scif_clk: scif {
  66                 compatible = "fixed-clock";
  67                 #clock-cells = <0>;
  68                 clock-frequency = <0>;
  69         };
  70
  71         soc {
  72                 compatible = "simple-bus";
  73                 interrupt-parent = <&gic>;
  74
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77                 ranges;
  78                 u-boot,dm-pre-reloc;
  79
  80                 gic: interrupt-controller@f1010000 {
  81                         compatible = "arm,gic-400";
  82                         #interrupt-cells = <3>;
  83                         #address-cells = <0>;
  84                         interrupt-controller;
  85                         reg = <0 0xf1010000 0 0x1000>,
  86                               <0 0xf1020000 0 0x20000>,
  87                               <0 0xf1040000 0 0x20000>,
  88                               <0 0xf1060000 0 0x20000>;
  89                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
  90                                       IRQ_TYPE_LEVEL_HIGH)>;
  91                         clocks = <&cpg CPG_MOD 408>;
  92                         clock-names = "clk";
  93                         power-domains = <&sysc 32>;
  94                         resets = <&cpg 408>;
  95                 };
  96
  97                 timer {
  98                         compatible = "arm,armv8-timer";
  99                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
 100                                                   IRQ_TYPE_LEVEL_LOW)>,
 101                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
 102                                                   IRQ_TYPE_LEVEL_LOW)>,
 103                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
 104                                                   IRQ_TYPE_LEVEL_LOW)>,
 105                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
 106                                                   IRQ_TYPE_LEVEL_LOW)>;
 107                 };
 108
 109                 cpg: clock-controller@e6150000 {
 110                         compatible = "renesas,r8a77970-cpg-mssr";
 111                         reg = <0 0xe6150000 0 0x1000>;
 112                         clocks = <&extal_clk>, <&extalr_clk>;
 113                         clock-names = "extal", "extalr";
 114                         #clock-cells = <2>;
 115                         #power-domain-cells = <0>;
 116                         #reset-cells = <1>;
 117                         u-boot,dm-pre-reloc;
 118                 };
 119
 120                 rst: reset-controller@e6160000 {
 121                         compatible = "renesas,r8a77970-rst";
 122                         reg = <0 0xe6160000 0 0x200>;
 123                 };
 124
 125                 sysc: system-controller@e6180000 {
 126                         compatible = "renesas,r8a77970-sysc";
 127                         reg = <0 0xe6180000 0 0x440>;
 128                         #power-domain-cells = <1>;
 129                 };
 130
 131                 pfc: pfc@e6060000 {
 132                         compatible = "renesas,pfc-r8a77970";
 133                         reg = <0 0xe6060000 0 0x50c>;
 134                 };
 135
 136                 intc_ex: interrupt-controller@e61c0000 {
 137                         compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
 138                         #interrupt-cells = <2>;
 139                         interrupt-controller;
 140                         reg = <0 0xe61c0000 0 0x200>;
 141                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 142                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 143                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 144                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 145                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 146                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&cpg CPG_MOD 407>;
 148                         power-domains = <&sysc 32>;
 149                         resets = <&cpg 407>;
 150                 };
 151
 152                 prr: chipid@fff00044 {
 153                         compatible = "renesas,prr";
 154                         reg = <0 0xfff00044 0 4>;
 155                         u-boot,dm-pre-reloc;
 156                 };
 157
 158                 dmac1: dma-controller@e7300000 {
 159                         compatible = "renesas,dmac-r8a77970",
 160                                      "renesas,rcar-dmac";
 161                         reg = <0 0xe7300000 0 0x10000>;
 162                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 163                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 164                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 165                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 166                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 167                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 168                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 169                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 170                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 171                         interrupt-names = "error",
 172                                           "ch0", "ch1", "ch2", "ch3",
 173                                           "ch4", "ch5", "ch6", "ch7";
 174                         clocks = <&cpg CPG_MOD 218>;
 175                         clock-names = "fck";
 176                         power-domains = <&sysc 32>;
 177                         resets = <&cpg 218>;
 178                         #dma-cells = <1>;
 179                         dma-channels = <8>;
 180                 };
 181
 182                 dmac2: dma-controller@e7310000 {
 183                         compatible = "renesas,dmac-r8a77970",
 184                                      "renesas,rcar-dmac";
 185                         reg = <0 0xe7310000 0 0x10000>;
 186                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 187                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 188                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 189                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 190                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 191                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 192                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 193                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 194                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 195                         interrupt-names = "error",
 196                                           "ch0", "ch1", "ch2", "ch3",
 197                                           "ch4", "ch5", "ch6", "ch7";
 198                         clocks = <&cpg CPG_MOD 217>;
 199                         clock-names = "fck";
 200                         power-domains = <&sysc 32>;
 201                         resets = <&cpg 217>;
 202                         #dma-cells = <1>;
 203                         dma-channels = <8>;
 204                 };
 205
 206                 hscif0: serial@e6540000 {
 207                         compatible = "renesas,hscif-r8a77970",
 208                                      "renesas,rcar-gen3-hscif",
 209                                      "renesas,hscif";
 210                         reg = <0 0xe6540000 0 96>;
 211                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&cpg CPG_MOD 520>,
 213                                  <&cpg CPG_CORE 9>,
 214                                  <&scif_clk>;
 215                         clock-names = "fck", "brg_int", "scif_clk";
 216                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 217                                <&dmac2 0x31>, <&dmac2 0x30>;
 218                         dma-names = "tx", "rx", "tx", "rx";
 219                         power-domains = <&sysc 32>;
 220                         resets = <&cpg 520>;
 221                         status = "disabled";
 222                 };
 223
 224                 hscif1: serial@e6550000 {
 225                         compatible = "renesas,hscif-r8a77970",
 226                                      "renesas,rcar-gen3-hscif",
 227                                      "renesas,hscif";
 228                         reg = <0 0xe6550000 0 96>;
 229                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 230                         clocks = <&cpg CPG_MOD 519>,
 231                                  <&cpg CPG_CORE 9>,
 232                                  <&scif_clk>;
 233                         clock-names = "fck", "brg_int", "scif_clk";
 234                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 235                                <&dmac2 0x33>, <&dmac2 0x32>;
 236                         dma-names = "tx", "rx", "tx", "rx";
 237                         power-domains = <&sysc 32>;
 238                         resets = <&cpg 519>;
 239                         status = "disabled";
 240                 };
 241
 242                 hscif2: serial@e6560000 {
 243                         compatible = "renesas,hscif-r8a77970",
 244                                      "renesas,rcar-gen3-hscif",
 245                                      "renesas,hscif";
 246                         reg = <0 0xe6560000 0 96>;
 247                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 248                         clocks = <&cpg CPG_MOD 518>,
 249                                  <&cpg CPG_CORE 9>,
 250                                  <&scif_clk>;
 251                         clock-names = "fck", "brg_int", "scif_clk";
 252                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 253                                <&dmac2 0x35>, <&dmac2 0x34>;
 254                         dma-names = "tx", "rx", "tx", "rx";
 255                         power-domains = <&sysc 32>;
 256                         resets = <&cpg 518>;
 257                         status = "disabled";
 258                 };
 259
 260                 hscif3: serial@e66a0000 {
 261                         compatible = "renesas,hscif-r8a77970",
 262                                      "renesas,rcar-gen3-hscif", "renesas,hscif";
 263                         reg = <0 0xe66a0000 0 96>;
 264                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 265                         clocks = <&cpg CPG_MOD 517>,
 266                                  <&cpg CPG_CORE 9>,
 267                                  <&scif_clk>;
 268                         clock-names = "fck", "brg_int", "scif_clk";
 269                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 270                                <&dmac2 0x37>, <&dmac2 0x36>;
 271                         dma-names = "tx", "rx", "tx", "rx";
 272                         power-domains = <&sysc 32>;
 273                         resets = <&cpg 517>;
 274                         status = "disabled";
 275                 };
 276
 277                 scif0: serial@e6e60000 {
 278                         compatible = "renesas,scif-r8a77970",
 279                                      "renesas,rcar-gen3-scif",
 280                                      "renesas,scif";
 281                         reg = <0 0xe6e60000 0 64>;
 282                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&cpg CPG_MOD 207>,
 284                                  <&cpg CPG_CORE 9>,
 285                                  <&scif_clk>;
 286                         clock-names = "fck", "brg_int", "scif_clk";
 287                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 288                                <&dmac2 0x51>, <&dmac2 0x50>;
 289                         dma-names = "tx", "rx", "tx", "rx";
 290                         power-domains = <&sysc 32>;
 291                         resets = <&cpg 207>;
 292                         status = "disabled";
 293                 };
 294
 295                 scif1: serial@e6e68000 {
 296                         compatible = "renesas,scif-r8a77970",
 297                                      "renesas,rcar-gen3-scif",
 298                                      "renesas,scif";
 299                         reg = <0 0xe6e68000 0 64>;
 300                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&cpg CPG_MOD 206>,
 302                                  <&cpg CPG_CORE 9>,
 303                                  <&scif_clk>;
 304                         clock-names = "fck", "brg_int", "scif_clk";
 305                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 306                                <&dmac2 0x53>, <&dmac2 0x52>;
 307                         dma-names = "tx", "rx", "tx", "rx";
 308                         power-domains = <&sysc 32>;
 309                         resets = <&cpg 206>;
 310                         status = "disabled";
 311                 };
 312
 313                 scif3: serial@e6c50000 {
 314                         compatible = "renesas,scif-r8a77970",
 315                                      "renesas,rcar-gen3-scif",
 316                                      "renesas,scif";
 317                         reg = <0 0xe6c50000 0 64>;
 318                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 319                         clocks = <&cpg CPG_MOD 204>,
 320                                  <&cpg CPG_CORE 9>,
 321                                  <&scif_clk>;
 322                         clock-names = "fck", "brg_int", "scif_clk";
 323                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 324                                <&dmac2 0x57>, <&dmac2 0x56>;
 325                         dma-names = "tx", "rx", "tx", "rx";
 326                         power-domains = <&sysc 32>;
 327                         resets = <&cpg 204>;
 328                         status = "disabled";
 329                 };
 330
 331                 scif4: serial@e6c40000 {
 332                         compatible = "renesas,scif-r8a77970",
 333                                      "renesas,rcar-gen3-scif", "renesas,scif";
 334                         reg = <0 0xe6c40000 0 64>;
 335                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&cpg CPG_MOD 203>,
 337                                  <&cpg CPG_CORE 9>,
 338                                  <&scif_clk>;
 339                         clock-names = "fck", "brg_int", "scif_clk";
 340                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 341                                <&dmac2 0x59>, <&dmac2 0x58>;
 342                         dma-names = "tx", "rx", "tx", "rx";
 343                         power-domains = <&sysc 32>;
 344                         resets = <&cpg 203>;
 345                         status = "disabled";
 346                 };
 347
 348                 avb: ethernet@e6800000 {
 349                         compatible = "renesas,etheravb-r8a77970",
 350                                      "renesas,etheravb-rcar-gen3";
 351                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 352                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 353                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 355                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 356                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 357                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 359                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 361                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 365                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 367                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 368                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 369                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 370                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 371                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 372                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 373                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 374                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 375                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 376                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 377                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 378                                           "ch4", "ch5", "ch6", "ch7",
 379                                           "ch8", "ch9", "ch10", "ch11",
 380                                           "ch12", "ch13", "ch14", "ch15",
 381                                           "ch16", "ch17", "ch18", "ch19",
 382                                           "ch20", "ch21", "ch22", "ch23",
 383                                           "ch24";
 384                         clocks = <&cpg CPG_MOD 812>;
 385                         power-domains = <&sysc 32>;
 386                         resets = <&cpg 812>;
 387                         phy-mode = "rgmii-id";
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                 };
 391         };
 392 };