arch/arm/dts/r8a7792.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R-Car V2H (R8A77920) SoC
   4  *
   5  * Copyright (C) 2016 Cogent Embedded Inc.
   6  */
   7
   8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/r8a7792-sysc.h>
  12
  13 / {
  14         compatible = "renesas,r8a7792";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 i2c5 = &i2c5;
  25                 spi0 = &qspi;
  26                 spi1 = &msiof0;
  27                 spi2 = &msiof1;
  28                 vin0 = &vin0;
  29                 vin1 = &vin1;
  30                 vin2 = &vin2;
  31                 vin3 = &vin3;
  32                 vin4 = &vin4;
  33                 vin5 = &vin5;
  34         };
  35
  36         /* External CAN clock */
  37         can_clk: can {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 /* This value must be overridden by the board. */
  41                 clock-frequency = <0>;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 enable-method = "renesas,apmu";
  48
  49                 cpu0: cpu@0 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a15";
  52                         reg = <0>;
  53                         clock-frequency = <1000000000>;
  54                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  55                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  56                         next-level-cache = <&L2_CA15>;
  57                 };
  58
  59                 cpu1: cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a15";
  62                         reg = <1>;
  63                         clock-frequency = <1000000000>;
  64                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  65                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  66                         next-level-cache = <&L2_CA15>;
  67                 };
  68
  69                 L2_CA15: cache-controller-0 {
  70                         compatible = "cache";
  71                         cache-unified;
  72                         cache-level = <2>;
  73                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  74                 };
  75         };
  76
  77         /* External root clock */
  78         extal_clk: extal {
  79                 compatible = "fixed-clock";
  80                 #clock-cells = <0>;
  81                 /* This value must be overridden by the board. */
  82                 clock-frequency = <0>;
  83         };
  84
  85         pmu {
  86                 compatible = "arm,cortex-a15-pmu";
  87                 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  88                                       <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  89                 interrupt-affinity = <&cpu0>, <&cpu1>;
  90         };
  91
  92         /* External SCIF clock */
  93         scif_clk: scif {
  94                 compatible = "fixed-clock";
  95                 #clock-cells = <0>;
  96                 /* This value must be overridden by the board. */
  97                 clock-frequency = <0>;
  98         };
  99
 100         soc {
 101                 compatible = "simple-bus";
 102                 interrupt-parent = <&gic>;
 103
 104                 #address-cells = <2>;
 105                 #size-cells = <2>;
 106                 ranges;
 107
 108                 rwdt: watchdog@e6020000 {
 109                         compatible = "renesas,r8a7792-wdt",
 110                                      "renesas,rcar-gen2-wdt";
 111                         reg = <0 0xe6020000 0 0x0c>;
 112                         clocks = <&cpg CPG_MOD 402>;
 113                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 114                         resets = <&cpg 402>;
 115                         status = "disabled";
 116                 };
 117
 118                 gpio0: gpio@e6050000 {
 119                         compatible = "renesas,gpio-r8a7792",
 120                                      "renesas,rcar-gen2-gpio";
 121                         reg = <0 0xe6050000 0 0x50>;
 122                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 123                         #gpio-cells = <2>;
 124                         gpio-controller;
 125                         gpio-ranges = <&pfc 0 0 29>;
 126                         #interrupt-cells = <2>;
 127                         interrupt-controller;
 128                         clocks = <&cpg CPG_MOD 912>;
 129                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 130                         resets = <&cpg 912>;
 131                 };
 132
 133                 gpio1: gpio@e6051000 {
 134                         compatible = "renesas,gpio-r8a7792",
 135                                      "renesas,rcar-gen2-gpio";
 136                         reg = <0 0xe6051000 0 0x50>;
 137                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 138                         #gpio-cells = <2>;
 139                         gpio-controller;
 140                         gpio-ranges = <&pfc 0 32 23>;
 141                         #interrupt-cells = <2>;
 142                         interrupt-controller;
 143                         clocks = <&cpg CPG_MOD 911>;
 144                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 145                         resets = <&cpg 911>;
 146                 };
 147
 148                 gpio2: gpio@e6052000 {
 149                         compatible = "renesas,gpio-r8a7792",
 150                                      "renesas,rcar-gen2-gpio";
 151                         reg = <0 0xe6052000 0 0x50>;
 152                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 153                         #gpio-cells = <2>;
 154                         gpio-controller;
 155                         gpio-ranges = <&pfc 0 64 32>;
 156                         #interrupt-cells = <2>;
 157                         interrupt-controller;
 158                         clocks = <&cpg CPG_MOD 910>;
 159                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 160                         resets = <&cpg 910>;
 161                 };
 162
 163                 gpio3: gpio@e6053000 {
 164                         compatible = "renesas,gpio-r8a7792",
 165                                      "renesas,rcar-gen2-gpio";
 166                         reg = <0 0xe6053000 0 0x50>;
 167                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 168                         #gpio-cells = <2>;
 169                         gpio-controller;
 170                         gpio-ranges = <&pfc 0 96 28>;
 171                         #interrupt-cells = <2>;
 172                         interrupt-controller;
 173                         clocks = <&cpg CPG_MOD 909>;
 174                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 175                         resets = <&cpg 909>;
 176                 };
 177
 178                 gpio4: gpio@e6054000 {
 179                         compatible = "renesas,gpio-r8a7792",
 180                                      "renesas,rcar-gen2-gpio";
 181                         reg = <0 0xe6054000 0 0x50>;
 182                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 183                         #gpio-cells = <2>;
 184                         gpio-controller;
 185                         gpio-ranges = <&pfc 0 128 17>;
 186                         #interrupt-cells = <2>;
 187                         interrupt-controller;
 188                         clocks = <&cpg CPG_MOD 908>;
 189                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 190                         resets = <&cpg 908>;
 191                 };
 192
 193                 gpio5: gpio@e6055000 {
 194                         compatible = "renesas,gpio-r8a7792",
 195                                      "renesas,rcar-gen2-gpio";
 196                         reg = <0 0xe6055000 0 0x50>;
 197                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 198                         #gpio-cells = <2>;
 199                         gpio-controller;
 200                         gpio-ranges = <&pfc 0 160 17>;
 201                         #interrupt-cells = <2>;
 202                         interrupt-controller;
 203                         clocks = <&cpg CPG_MOD 907>;
 204                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 205                         resets = <&cpg 907>;
 206                 };
 207
 208                 gpio6: gpio@e6055100 {
 209                         compatible = "renesas,gpio-r8a7792",
 210                                      "renesas,rcar-gen2-gpio";
 211                         reg = <0 0xe6055100 0 0x50>;
 212                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 213                         #gpio-cells = <2>;
 214                         gpio-controller;
 215                         gpio-ranges = <&pfc 0 192 17>;
 216                         #interrupt-cells = <2>;
 217                         interrupt-controller;
 218                         clocks = <&cpg CPG_MOD 905>;
 219                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 220                         resets = <&cpg 905>;
 221                 };
 222
 223                 gpio7: gpio@e6055200 {
 224                         compatible = "renesas,gpio-r8a7792",
 225                                      "renesas,rcar-gen2-gpio";
 226                         reg = <0 0xe6055200 0 0x50>;
 227                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 228                         #gpio-cells = <2>;
 229                         gpio-controller;
 230                         gpio-ranges = <&pfc 0 224 17>;
 231                         #interrupt-cells = <2>;
 232                         interrupt-controller;
 233                         clocks = <&cpg CPG_MOD 904>;
 234                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 235                         resets = <&cpg 904>;
 236                 };
 237
 238                 gpio8: gpio@e6055300 {
 239                         compatible = "renesas,gpio-r8a7792",
 240                                      "renesas,rcar-gen2-gpio";
 241                         reg = <0 0xe6055300 0 0x50>;
 242                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 243                         #gpio-cells = <2>;
 244                         gpio-controller;
 245                         gpio-ranges = <&pfc 0 256 17>;
 246                         #interrupt-cells = <2>;
 247                         interrupt-controller;
 248                         clocks = <&cpg CPG_MOD 921>;
 249                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 250                         resets = <&cpg 921>;
 251                 };
 252
 253                 gpio9: gpio@e6055400 {
 254                         compatible = "renesas,gpio-r8a7792",
 255                                      "renesas,rcar-gen2-gpio";
 256                         reg = <0 0xe6055400 0 0x50>;
 257                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 258                         #gpio-cells = <2>;
 259                         gpio-controller;
 260                         gpio-ranges = <&pfc 0 288 17>;
 261                         #interrupt-cells = <2>;
 262                         interrupt-controller;
 263                         clocks = <&cpg CPG_MOD 919>;
 264                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 265                         resets = <&cpg 919>;
 266                 };
 267
 268                 gpio10: gpio@e6055500 {
 269                         compatible = "renesas,gpio-r8a7792",
 270                                      "renesas,rcar-gen2-gpio";
 271                         reg = <0 0xe6055500 0 0x50>;
 272                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 273                         #gpio-cells = <2>;
 274                         gpio-controller;
 275                         gpio-ranges = <&pfc 0 320 32>;
 276                         #interrupt-cells = <2>;
 277                         interrupt-controller;
 278                         clocks = <&cpg CPG_MOD 914>;
 279                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 280                         resets = <&cpg 914>;
 281                 };
 282
 283                 gpio11: gpio@e6055600 {
 284                         compatible = "renesas,gpio-r8a7792",
 285                                      "renesas,rcar-gen2-gpio";
 286                         reg = <0 0xe6055600 0 0x50>;
 287                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 288                         #gpio-cells = <2>;
 289                         gpio-controller;
 290                         gpio-ranges = <&pfc 0 352 30>;
 291                         #interrupt-cells = <2>;
 292                         interrupt-controller;
 293                         clocks = <&cpg CPG_MOD 913>;
 294                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 295                         resets = <&cpg 913>;
 296                 };
 297
 298                 pfc: pin-controller@e6060000 {
 299                         compatible = "renesas,pfc-r8a7792";
 300                         reg = <0 0xe6060000 0 0x144>;
 301                 };
 302
 303                 cpg: clock-controller@e6150000 {
 304                         compatible = "renesas,r8a7792-cpg-mssr";
 305                         reg = <0 0xe6150000 0 0x1000>;
 306                         clocks = <&extal_clk>;
 307                         clock-names = "extal";
 308                         #clock-cells = <2>;
 309                         #power-domain-cells = <0>;
 310                         #reset-cells = <1>;
 311                 };
 312
 313                 apmu@e6152000 {
 314                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
 315                         reg = <0 0xe6152000 0 0x188>;
 316                         cpus = <&cpu0 &cpu1>;
 317                 };
 318
 319                 rst: reset-controller@e6160000 {
 320                         compatible = "renesas,r8a7792-rst";
 321                         reg = <0 0xe6160000 0 0x0100>;
 322                 };
 323
 324                 sysc: system-controller@e6180000 {
 325                         compatible = "renesas,r8a7792-sysc";
 326                         reg = <0 0xe6180000 0 0x0200>;
 327                         #power-domain-cells = <1>;
 328                 };
 329
 330                 irqc: interrupt-controller@e61c0000 {
 331                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
 332                         #interrupt-cells = <2>;
 333                         interrupt-controller;
 334                         reg = <0 0xe61c0000 0 0x200>;
 335                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 337                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 338                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 339                         clocks = <&cpg CPG_MOD 407>;
 340                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 341                         resets = <&cpg 407>;
 342                 };
 343
 344                 icram0: sram@e63a0000 {
 345                         compatible = "mmio-sram";
 346                         reg = <0 0xe63a0000 0 0x12000>;
 347                 };
 348
 349                 icram1: sram@e63c0000 {
 350                         compatible = "mmio-sram";
 351                         reg = <0 0xe63c0000 0 0x1000>;
 352                         #address-cells = <1>;
 353                         #size-cells = <1>;
 354                         ranges = <0 0 0xe63c0000 0x1000>;
 355
 356                         smp-sram@0 {
 357                                 compatible = "renesas,smp-sram";
 358                                 reg = <0 0x100>;
 359                         };
 360                 };
 361
 362                 /* I2C doesn't need pinmux */
 363                 i2c0: i2c@e6508000 {
 364                         compatible = "renesas,i2c-r8a7792",
 365                                      "renesas,rcar-gen2-i2c";
 366                         reg = <0 0xe6508000 0 0x40>;
 367                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&cpg CPG_MOD 931>;
 369                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 370                         resets = <&cpg 931>;
 371                         i2c-scl-internal-delay-ns = <6>;
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         status = "disabled";
 375                 };
 376
 377                 i2c1: i2c@e6518000 {
 378                         compatible = "renesas,i2c-r8a7792",
 379                                      "renesas,rcar-gen2-i2c";
 380                         reg = <0 0xe6518000 0 0x40>;
 381                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&cpg CPG_MOD 930>;
 383                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 384                         resets = <&cpg 930>;
 385                         i2c-scl-internal-delay-ns = <6>;
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         status = "disabled";
 389                 };
 390
 391                 i2c2: i2c@e6530000 {
 392                         compatible = "renesas,i2c-r8a7792",
 393                                      "renesas,rcar-gen2-i2c";
 394                         reg = <0 0xe6530000 0 0x40>;
 395                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&cpg CPG_MOD 929>;
 397                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 398                         resets = <&cpg 929>;
 399                         i2c-scl-internal-delay-ns = <6>;
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         status = "disabled";
 403                 };
 404
 405                 i2c3: i2c@e6540000 {
 406                         compatible = "renesas,i2c-r8a7792",
 407                                      "renesas,rcar-gen2-i2c";
 408                         reg = <0 0xe6540000 0 0x40>;
 409                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&cpg CPG_MOD 928>;
 411                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 412                         resets = <&cpg 928>;
 413                         i2c-scl-internal-delay-ns = <6>;
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         status = "disabled";
 417                 };
 418
 419                 i2c4: i2c@e6520000 {
 420                         compatible = "renesas,i2c-r8a7792",
 421                                      "renesas,rcar-gen2-i2c";
 422                         reg = <0 0xe6520000 0 0x40>;
 423                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&cpg CPG_MOD 927>;
 425                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 426                         resets = <&cpg 927>;
 427                         i2c-scl-internal-delay-ns = <6>;
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         status = "disabled";
 431                 };
 432
 433                 i2c5: i2c@e6528000 {
 434                         compatible = "renesas,i2c-r8a7792",
 435                                      "renesas,rcar-gen2-i2c";
 436                         reg = <0 0xe6528000 0 0x40>;
 437                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&cpg CPG_MOD 925>;
 439                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 440                         resets = <&cpg 925>;
 441                         i2c-scl-internal-delay-ns = <110>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         status = "disabled";
 445                 };
 446
 447                 iic3: i2c@e60b0000 {
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         compatible = "renesas,iic-r8a7792",
 451                                      "renesas,rcar-gen2-iic",
 452                                      "renesas,rmobile-iic";
 453                         reg = <0 0xe60b0000 0 0x425>;
 454                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&cpg CPG_MOD 926>;
 456                         dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 457                                <&dmac1 0x77>, <&dmac1 0x78>;
 458                         dma-names = "tx", "rx", "tx", "rx";
 459                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 460                         resets = <&cpg 926>;
 461                         status = "disabled";
 462                 };
 463
 464                 dmac0: dma-controller@e6700000 {
 465                         compatible = "renesas,dmac-r8a7792",
 466                                      "renesas,rcar-dmac";
 467                         reg = <0 0xe6700000 0 0x20000>;
 468                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 469                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 470                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 471                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 472                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 473                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 474                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 475                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 476                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 477                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 478                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 479                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 480                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 481                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 482                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 483                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 484                         interrupt-names = "error",
 485                                           "ch0", "ch1", "ch2", "ch3",
 486                                           "ch4", "ch5", "ch6", "ch7",
 487                                           "ch8", "ch9", "ch10", "ch11",
 488                                           "ch12", "ch13", "ch14";
 489                         clocks = <&cpg CPG_MOD 219>;
 490                         clock-names = "fck";
 491                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 492                         resets = <&cpg 219>;
 493                         #dma-cells = <1>;
 494                         dma-channels = <15>;
 495                 };
 496
 497                 dmac1: dma-controller@e6720000 {
 498                         compatible = "renesas,dmac-r8a7792",
 499                                      "renesas,rcar-dmac";
 500                         reg = <0 0xe6720000 0 0x20000>;
 501                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 502                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 503                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 504                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 505                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 506                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 507                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 508                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 509                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 510                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 511                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 512                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 513                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 514                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 515                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 516                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 517                         interrupt-names = "error",
 518                                           "ch0", "ch1", "ch2", "ch3",
 519                                           "ch4", "ch5", "ch6", "ch7",
 520                                           "ch8", "ch9", "ch10", "ch11",
 521                                           "ch12", "ch13", "ch14";
 522                         clocks = <&cpg CPG_MOD 218>;
 523                         clock-names = "fck";
 524                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 525                         resets = <&cpg 218>;
 526                         #dma-cells = <1>;
 527                         dma-channels = <15>;
 528                 };
 529
 530                 avb: ethernet@e6800000 {
 531                         compatible = "renesas,etheravb-r8a7792",
 532                                      "renesas,etheravb-rcar-gen2";
 533                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 534                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 535                         clocks = <&cpg CPG_MOD 812>;
 536                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 537                         resets = <&cpg 812>;
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         status = "disabled";
 541                 };
 542
 543                 qspi: spi@e6b10000 {
 544                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 545                         reg = <0 0xe6b10000 0 0x2c>;
 546                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&cpg CPG_MOD 917>;
 548                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 549                                <&dmac1 0x17>, <&dmac1 0x18>;
 550                         dma-names = "tx", "rx", "tx", "rx";
 551                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 552                         resets = <&cpg 917>;
 553                         num-cs = <1>;
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         status = "disabled";
 557                 };
 558
 559                 scif0: serial@e6e60000 {
 560                         compatible = "renesas,scif-r8a7792",
 561                                      "renesas,rcar-gen2-scif", "renesas,scif";
 562                         reg = <0 0xe6e60000 0 64>;
 563                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&cpg CPG_MOD 721>,
 565                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 566                         clock-names = "fck", "brg_int", "scif_clk";
 567                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 568                                <&dmac1 0x29>, <&dmac1 0x2a>;
 569                         dma-names = "tx", "rx", "tx", "rx";
 570                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 571                         resets = <&cpg 721>;
 572                         status = "disabled";
 573                 };
 574
 575                 scif1: serial@e6e68000 {
 576                         compatible = "renesas,scif-r8a7792",
 577                                      "renesas,rcar-gen2-scif", "renesas,scif";
 578                         reg = <0 0xe6e68000 0 64>;
 579                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&cpg CPG_MOD 720>,
 581                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 582                         clock-names = "fck", "brg_int", "scif_clk";
 583                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 584                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 585                         dma-names = "tx", "rx", "tx", "rx";
 586                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 587                         resets = <&cpg 720>;
 588                         status = "disabled";
 589                 };
 590
 591                 scif2: serial@e6e58000 {
 592                         compatible = "renesas,scif-r8a7792",
 593                                      "renesas,rcar-gen2-scif", "renesas,scif";
 594                         reg = <0 0xe6e58000 0 64>;
 595                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 596                         clocks = <&cpg CPG_MOD 719>,
 597                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 598                         clock-names = "fck", "brg_int", "scif_clk";
 599                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 600                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 601                         dma-names = "tx", "rx", "tx", "rx";
 602                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 603                         resets = <&cpg 719>;
 604                         status = "disabled";
 605                 };
 606
 607                 scif3: serial@e6ea8000 {
 608                         compatible = "renesas,scif-r8a7792",
 609                                      "renesas,rcar-gen2-scif", "renesas,scif";
 610                         reg = <0 0xe6ea8000 0 64>;
 611                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&cpg CPG_MOD 718>,
 613                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 614                         clock-names = "fck", "brg_int", "scif_clk";
 615                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 616                                <&dmac1 0x2f>, <&dmac1 0x30>;
 617                         dma-names = "tx", "rx", "tx", "rx";
 618                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 619                         resets = <&cpg 718>;
 620                         status = "disabled";
 621                 };
 622
 623                 hscif0: serial@e62c0000 {
 624                         compatible = "renesas,hscif-r8a7792",
 625                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 626                         reg = <0 0xe62c0000 0 96>;
 627                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 628                         clocks = <&cpg CPG_MOD 717>,
 629                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 630                         clock-names = "fck", "brg_int", "scif_clk";
 631                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 632                                <&dmac1 0x39>, <&dmac1 0x3a>;
 633                         dma-names = "tx", "rx", "tx", "rx";
 634                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 635                         resets = <&cpg 717>;
 636                         status = "disabled";
 637                 };
 638
 639                 hscif1: serial@e62c8000 {
 640                         compatible = "renesas,hscif-r8a7792",
 641                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 642                         reg = <0 0xe62c8000 0 96>;
 643                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 644                         clocks = <&cpg CPG_MOD 716>,
 645                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 646                         clock-names = "fck", "brg_int", "scif_clk";
 647                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 648                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 649                         dma-names = "tx", "rx", "tx", "rx";
 650                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 651                         resets = <&cpg 716>;
 652                         status = "disabled";
 653                 };
 654
 655                 msiof0: spi@e6e20000 {
 656                         compatible = "renesas,msiof-r8a7792",
 657                                      "renesas,rcar-gen2-msiof";
 658                         reg = <0 0xe6e20000 0 0x0064>;
 659                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&cpg CPG_MOD 000>;
 661                         dmas = <&dmac0 0x51>, <&dmac0 0x52>,
 662                                <&dmac1 0x51>, <&dmac1 0x52>;
 663                         dma-names = "tx", "rx", "tx", "rx";
 664                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 665                         resets = <&cpg 000>;
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                         status = "disabled";
 669                 };
 670
 671                 msiof1: spi@e6e10000 {
 672                         compatible = "renesas,msiof-r8a7792",
 673                                      "renesas,rcar-gen2-msiof";
 674                         reg = <0 0xe6e10000 0 0x0064>;
 675                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 676                         clocks = <&cpg CPG_MOD 208>;
 677                         dmas = <&dmac0 0x55>, <&dmac0 0x56>,
 678                                <&dmac1 0x55>, <&dmac1 0x56>;
 679                         dma-names = "tx", "rx", "tx", "rx";
 680                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 681                         resets = <&cpg 208>;
 682                         #address-cells = <1>;
 683                         #size-cells = <0>;
 684                         status = "disabled";
 685                 };
 686
 687                 can0: can@e6e80000 {
 688                         compatible = "renesas,can-r8a7792",
 689                                      "renesas,rcar-gen2-can";
 690                         reg = <0 0xe6e80000 0 0x1000>;
 691                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&cpg CPG_MOD 916>,
 693                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 694                         clock-names = "clkp1", "clkp2", "can_clk";
 695                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 696                         resets = <&cpg 916>;
 697                         status = "disabled";
 698                 };
 699
 700                 can1: can@e6e88000 {
 701                         compatible = "renesas,can-r8a7792",
 702                                      "renesas,rcar-gen2-can";
 703                         reg = <0 0xe6e88000 0 0x1000>;
 704                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 705                         clocks = <&cpg CPG_MOD 915>,
 706                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 707                         clock-names = "clkp1", "clkp2", "can_clk";
 708                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 709                         resets = <&cpg 915>;
 710                         status = "disabled";
 711                 };
 712
 713                 vin0: video@e6ef0000 {
 714                         compatible = "renesas,vin-r8a7792",
 715                                      "renesas,rcar-gen2-vin";
 716                         reg = <0 0xe6ef0000 0 0x1000>;
 717                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 718                         clocks = <&cpg CPG_MOD 811>;
 719                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 720                         resets = <&cpg 811>;
 721                         status = "disabled";
 722                 };
 723
 724                 vin1: video@e6ef1000 {
 725                         compatible = "renesas,vin-r8a7792",
 726                                      "renesas,rcar-gen2-vin";
 727                         reg = <0 0xe6ef1000 0 0x1000>;
 728                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 729                         clocks = <&cpg CPG_MOD 810>;
 730                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 731                         resets = <&cpg 810>;
 732                         status = "disabled";
 733                 };
 734
 735                 vin2: video@e6ef2000 {
 736                         compatible = "renesas,vin-r8a7792",
 737                                      "renesas,rcar-gen2-vin";
 738                         reg = <0 0xe6ef2000 0 0x1000>;
 739                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 740                         clocks = <&cpg CPG_MOD 809>;
 741                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 742                         resets = <&cpg 809>;
 743                         status = "disabled";
 744                 };
 745
 746                 vin3: video@e6ef3000 {
 747                         compatible = "renesas,vin-r8a7792",
 748                                      "renesas,rcar-gen2-vin";
 749                         reg = <0 0xe6ef3000 0 0x1000>;
 750                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 751                         clocks = <&cpg CPG_MOD 808>;
 752                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 753                         resets = <&cpg 808>;
 754                         status = "disabled";
 755                 };
 756
 757                 vin4: video@e6ef4000 {
 758                         compatible = "renesas,vin-r8a7792",
 759                                      "renesas,rcar-gen2-vin";
 760                         reg = <0 0xe6ef4000 0 0x1000>;
 761                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 762                         clocks = <&cpg CPG_MOD 805>;
 763                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 764                         resets = <&cpg 805>;
 765                         status = "disabled";
 766                 };
 767
 768                 vin5: video@e6ef5000 {
 769                         compatible = "renesas,vin-r8a7792",
 770                                      "renesas,rcar-gen2-vin";
 771                         reg = <0 0xe6ef5000 0 0x1000>;
 772                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 773                         clocks = <&cpg CPG_MOD 804>;
 774                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 775                         resets = <&cpg 804>;
 776                         status = "disabled";
 777                 };
 778
 779                 sdhi0: sd@ee100000 {
 780                         compatible = "renesas,sdhi-r8a7792",
 781                                      "renesas,rcar-gen2-sdhi";
 782                         reg = <0 0xee100000 0 0x328>;
 783                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 784                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 785                                <&dmac1 0xcd>, <&dmac1 0xce>;
 786                         dma-names = "tx", "rx", "tx", "rx";
 787                         clocks = <&cpg CPG_MOD 314>;
 788                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 789                         resets = <&cpg 314>;
 790                         status = "disabled";
 791                 };
 792
 793                 gic: interrupt-controller@f1001000 {
 794                         compatible = "arm,gic-400";
 795                         #interrupt-cells = <3>;
 796                         interrupt-controller;
 797                         reg = <0 0xf1001000 0 0x1000>,
 798                               <0 0xf1002000 0 0x2000>,
 799                               <0 0xf1004000 0 0x2000>,
 800                               <0 0xf1006000 0 0x2000>;
 801                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 802                                       IRQ_TYPE_LEVEL_HIGH)>;
 803                         clocks = <&cpg CPG_MOD 408>;
 804                         clock-names = "clk";
 805                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 806                         resets = <&cpg 408>;
 807                 };
 808
 809                 vsp@fe928000 {
 810                         compatible = "renesas,vsp1";
 811                         reg = <0 0xfe928000 0 0x8000>;
 812                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 813                         clocks = <&cpg CPG_MOD 131>;
 814                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 815                         resets = <&cpg 131>;
 816                 };
 817
 818                 vsp@fe930000 {
 819                         compatible = "renesas,vsp1";
 820                         reg = <0 0xfe930000 0 0x8000>;
 821                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 822                         clocks = <&cpg CPG_MOD 128>;
 823                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 824                         resets = <&cpg 128>;
 825                 };
 826
 827                 vsp@fe938000 {
 828                         compatible = "renesas,vsp1";
 829                         reg = <0 0xfe938000 0 0x8000>;
 830                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 831                         clocks = <&cpg CPG_MOD 127>;
 832                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 833                         resets = <&cpg 127>;
 834                 };
 835
 836                 jpu: jpeg-codec@fe980000 {
 837                         compatible = "renesas,jpu-r8a7792",
 838                                      "renesas,rcar-gen2-jpu";
 839                         reg = <0 0xfe980000 0 0x10300>;
 840                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 841                         clocks = <&cpg CPG_MOD 106>;
 842                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 843                         resets = <&cpg 106>;
 844                 };
 845
 846                 du: display@feb00000 {
 847                         compatible = "renesas,du-r8a7792";
 848                         reg = <0 0xfeb00000 0 0x40000>;
 849                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 850                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 851                         clocks = <&cpg CPG_MOD 724>,
 852                                  <&cpg CPG_MOD 723>;
 853                         clock-names = "du.0", "du.1";
 854                         status = "disabled";
 855
 856                         ports {
 857                                 #address-cells = <1>;
 858                                 #size-cells = <0>;
 859
 860                                 port@0 {
 861                                         reg = <0>;
 862                                         du_out_rgb0: endpoint {
 863                                         };
 864                                 };
 865                                 port@1 {
 866                                         reg = <1>;
 867                                         du_out_rgb1: endpoint {
 868                                         };
 869                                 };
 870                         };
 871                 };
 872
 873                 prr: chipid@ff000044 {
 874                         compatible = "renesas,prr";
 875                         reg = <0 0xff000044 0 4>;
 876                 };
 877         };
 878
 879         timer {
 880                 compatible = "arm,armv7-timer";
 881                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 882                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 883                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 884                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 885         };
 886 };