arch/arm/dts/mt7629.dtsi

   1 /*
   2  * Copyright (C) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/clock/mt7629-clk.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/power/mt7629-power.h>
  13 #include <dt-bindings/reset/mt7629-reset.h>
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         compatible = "mediatek,mt7629";
  18         interrupt-parent = <&sysirq>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25                 enable-method = "mediatek,mt6589-smp";
  26
  27                 cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0x0>;
  31                         clock-frequency = <1250000000>;
  32                 };
  33
  34                 cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         reg = <0x1>;
  38                         clock-frequency = <1250000000>;
  39                 };
  40         };
  41
  42         clk20m: oscillator@0 {
  43                 compatible = "fixed-clock";
  44                 #clock-cells = <0>;
  45                 clock-frequency = <20000000>;
  46                 clock-output-names = "clk20m";
  47         };
  48
  49         clk40m: oscillator@1 {
  50                 compatible = "fixed-clock";
  51                 #clock-cells = <0>;
  52                 clock-frequency = <40000000>;
  53                 clock-output-names = "clkxtal";
  54         };
  55
  56         timer {
  57                 compatible = "arm,armv7-timer";
  58                 interrupt-parent = <&gic>;
  59                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  60                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  61                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  63                 clock-frequency = <20000000>;
  64                 arm,cpu-registers-not-fw-configured;
  65         };
  66
  67         infracfg: syscon@10000000 {
  68                 compatible = "mediatek,mt7629-infracfg", "syscon";
  69                 reg = <0x10000000 0x1000>;
  70                 #clock-cells = <1>;
  71         };
  72
  73         pericfg: syscon@10002000 {
  74                 compatible = "mediatek,mt7629-pericfg", "syscon";
  75                 reg = <0x10002000 0x1000>;
  76                 #clock-cells = <1>;
  77         };
  78
  79         timer0: timer@10004000 {
  80                 compatible = "mediatek,timer";
  81                 reg = <0x10004000 0x80>;
  82                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
  83                 clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
  84                          <&topckgen CLK_TOP_10M_SEL>;
  85                 clock-names = "mux", "src";
  86         };
  87
  88         scpsys: scpsys@10006000 {
  89                 compatible = "mediatek,mt7629-scpsys";
  90                 reg = <0x10006000 0x1000>;
  91                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
  92                 clock-names = "hif_sel";
  93                 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
  94                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
  95                 #power-domain-cells = <1>;
  96                 infracfg = <&infracfg>;
  97         };
  98
  99         mcucfg: syscon@10200000 {
 100                 compatible = "mediatek,mt7629-mcucfg", "syscon";
 101                 reg = <0x10200000 0x1000>;
 102                 #clock-cells = <1>;
 103         };
 104
 105         sysirq: interrupt-controller@10200a80 {
 106                 compatible = "mediatek,sysirq";
 107                 reg = <0x10200a80 0x20>;
 108                 interrupt-controller;
 109                 #interrupt-cells = <3>;
 110                 interrupt-parent = <&gic>;
 111         };
 112
 113         dramc: dramc@10203000 {
 114                 compatible = "mediatek,mt7629-dramc";
 115                 reg = <0x10203000 0x600>,       /* EMI */
 116                       <0x10213000 0x1000>,      /* DDRPHY */
 117                       <0x10214000 0xd00>;       /* DRAMC_AO */
 118                 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
 119                          <&topckgen CLK_TOP_SYSPLL1_D8>,
 120                          <&topckgen CLK_TOP_MEM_SEL>,
 121                          <&topckgen CLK_TOP_DMPLL>;
 122                 clock-names = "phy", "phy_mux", "mem", "mem_mux";
 123         };
 124
 125         apmixedsys: clock-controller@10209000 {
 126                 compatible = "mediatek,mt7629-apmixedsys";
 127                 reg = <0x10209000 0x1000>;
 128                 #clock-cells = <1>;
 129         };
 130
 131         topckgen: clock-controller@10210000 {
 132                 compatible = "mediatek,mt7629-topckgen";
 133                 reg = <0x10210000 0x1000>;
 134                 #clock-cells = <1>;
 135         };
 136
 137         watchdog: watchdog@10212000 {
 138                 compatible = "mediatek,wdt";
 139                 reg = <0x10212000 0x600>;
 140                 interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>;
 141                 #reset-cells = <1>;
 142                 status = "disabled";
 143         };
 144
 145         wdt-reboot {
 146                 compatible = "wdt-reboot";
 147                 wdt = <&watchdog>;
 148         };
 149
 150         pinctrl: pinctrl@10217000 {
 151                 compatible = "mediatek,mt7629-pinctrl";
 152                 reg = <0x10217000 0x8000>;
 153
 154                 gpio: gpio-controller {
 155                         gpio-controller;
 156                         #gpio-cells = <2>;
 157                 };
 158         };
 159
 160         gic: interrupt-controller@10300000 {
 161                 compatible = "arm,gic-400";
 162                 interrupt-controller;
 163                 #interrupt-cells = <3>;
 164                 interrupt-parent = <&gic>;
 165                 reg = <0x10310000 0x1000>,
 166                       <0x10320000 0x1000>,
 167                       <0x10340000 0x2000>,
 168                       <0x10360000 0x2000>;
 169         };
 170
 171         uart0: serial@11002000 {
 172                 compatible = "mediatek,hsuart";
 173                 reg = <0x11002000 0x400>;
 174                 reg-shift = <2>;
 175                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 176                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 177                          <&pericfg CLK_PERI_UART0_PD>;
 178                 clock-names = "baud", "bus";
 179                 status = "disabled";
 180                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 181                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 182         };
 183
 184         uart1: serial@11003000 {
 185                 compatible = "mediatek,hsuart";
 186                 reg = <0x11003000 0x400>;
 187                 reg-shift = <2>;
 188                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 189                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 190                          <&pericfg CLK_PERI_UART1_PD>;
 191                 clock-names = "baud", "bus";
 192                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 193                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 194                 status = "disabled";
 195         };
 196
 197         uart2: serial@11004000 {
 198                 compatible = "mediatek,hsuart";
 199                 reg = <0x11004000 0x400>;
 200                 reg-shift = <2>;
 201                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 202                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 203                          <&pericfg CLK_PERI_UART2_PD>;
 204                 clock-names = "baud", "bus";
 205                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 206                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 207                 status = "disabled";
 208         };
 209
 210         snfi: snfi@1100d000 {
 211                 compatible = "mediatek,mtk-snfi-spi";
 212                 reg = <0x1100d000 0x2000>;
 213                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 214                          <&pericfg CLK_PERI_SNFI_PD>;
 215                 clock-names = "nfi_clk", "pad_clk";
 216                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
 217                                   <&topckgen CLK_TOP_NFI_INFRA_SEL>;
 218                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
 219                                          <&topckgen CLK_TOP_UNIVPLL2_D8>;
 220                 status = "disabled";
 221                 #address-cells = <1>;
 222                 #size-cells = <0>;
 223         };
 224
 225         ethsys: syscon@1b000000 {
 226                 compatible = "mediatek,mt7629-ethsys", "syscon";
 227                 reg = <0x1b000000 0x1000>;
 228                 #clock-cells = <1>;
 229                 #reset-cells = <1>;
 230         };
 231
 232         eth: ethernet@1b100000 {
 233                 compatible = "mediatek,mt7629-eth", "syscon";
 234                 reg = <0x1b100000 0x20000>;
 235                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 236                         <&topckgen CLK_TOP_F10M_REF_SEL>,
 237                         <&ethsys CLK_ETH_ESW_EN>,
 238                         <&ethsys CLK_ETH_GP0_EN>,
 239                         <&ethsys CLK_ETH_GP1_EN>,
 240                         <&ethsys CLK_ETH_GP2_EN>,
 241                         <&ethsys CLK_ETH_FE_EN>,
 242                         <&sgmiisys0 CLK_SGMII_TX_EN>,
 243                         <&sgmiisys0 CLK_SGMII_RX_EN>,
 244                         <&sgmiisys0 CLK_SGMII_CDR_REF>,
 245                         <&sgmiisys0 CLK_SGMII_CDR_FB>,
 246                         <&sgmiisys1 CLK_SGMII_TX_EN>,
 247                         <&sgmiisys1 CLK_SGMII_RX_EN>,
 248                         <&sgmiisys1 CLK_SGMII_CDR_REF>,
 249                         <&sgmiisys1 CLK_SGMII_CDR_FB>,
 250                         <&apmixedsys CLK_APMIXED_SGMIPLL>,
 251                         <&apmixedsys CLK_APMIXED_ETH2PLL>;
 252                 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
 253                                 "fe", "sgmii_tx250m", "sgmii_rx250m",
 254                                 "sgmii_cdr_ref", "sgmii_cdr_fb",
 255                                 "sgmii2_tx250m", "sgmii2_rx250m",
 256                                 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 257                                 "sgmii_ck", "eth2pll";
 258                 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
 259                                   <&topckgen CLK_TOP_F10M_REF_SEL>;
 260                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
 261                                          <&topckgen CLK_TOP_SGMIIPLL_D2>;
 262                 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 263                 resets = <&ethsys ETHSYS_FE_RST>;
 264                 reset-names = "fe";
 265                 mediatek,ethsys = <&ethsys>;
 266                 mediatek,sgmiisys = <&sgmiisys0>;
 267                 mediatek,infracfg = <&infracfg>;
 268                 #address-cells = <1>;
 269                 #size-cells = <0>;
 270                 status = "disabled";
 271         };
 272
 273         sgmiisys0: syscon@1b128000 {
 274                 compatible = "mediatek,mt7629-sgmiisys", "syscon";
 275                 reg = <0x1b128000 0x1000>;
 276                 #clock-cells = <1>;
 277         };
 278
 279         sgmiisys1: syscon@1b130000 {
 280                 compatible = "mediatek,mt7629-sgmiisys", "syscon";
 281                 reg = <0x1b130000 0x1000>;
 282                 #clock-cells = <1>;
 283         };
 284 };