arch/arm/dts/mt7629.dtsi

   1 /*
   2  * Copyright (C) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/clock/mt7629-clk.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/power/mt7629-power.h>
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "mediatek,mt7629";
  17         interrupt-parent = <&sysirq>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 enable-method = "mediatek,mt6589-smp";
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0x0>;
  30                         clock-frequency = <1250000000>;
  31                 };
  32
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <0x1>;
  37                         clock-frequency = <1250000000>;
  38                 };
  39         };
  40
  41         clk20m: oscillator@0 {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <20000000>;
  45                 clock-output-names = "clk20m";
  46         };
  47
  48         clk40m: oscillator@1 {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <40000000>;
  52                 clock-output-names = "clkxtal";
  53         };
  54
  55         timer {
  56                 compatible = "arm,armv7-timer";
  57                 interrupt-parent = <&gic>;
  58                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  59                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  60                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  61                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  62                 clock-frequency = <20000000>;
  63                 arm,cpu-registers-not-fw-configured;
  64         };
  65
  66         infracfg: syscon@10000000 {
  67                 compatible = "mediatek,mt7629-infracfg", "syscon";
  68                 reg = <0x10000000 0x1000>;
  69                 #clock-cells = <1>;
  70                 u-boot,dm-pre-reloc;
  71         };
  72
  73         pericfg: syscon@10002000 {
  74                 compatible = "mediatek,mt7629-pericfg", "syscon";
  75                 reg = <0x10002000 0x1000>;
  76                 #clock-cells = <1>;
  77                 u-boot,dm-pre-reloc;
  78         };
  79
  80         timer0: timer@10004000 {
  81                 compatible = "mediatek,timer";
  82                 reg = <0x10004000 0x80>;
  83                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
  84                 clocks = <&topckgen CLK_TOP_10M_SEL>,
  85                          <&topckgen CLK_TOP_CLKXTAL_D4>;
  86                 clock-names = "mux", "src";
  87                 u-boot,dm-pre-reloc;
  88         };
  89
  90         scpsys: scpsys@10006000 {
  91                 compatible = "mediatek,mt7629-scpsys";
  92                 reg = <0x10006000 0x1000>;
  93                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
  94                 clock-names = "hif_sel";
  95                 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
  96                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
  97                 #power-domain-cells = <1>;
  98                 infracfg = <&infracfg>;
  99         };
 100
 101         mcucfg: syscon@10200000 {
 102                 compatible = "mediatek,mt7629-mcucfg", "syscon";
 103                 reg = <0x10200000 0x1000>;
 104                 #clock-cells = <1>;
 105                 u-boot,dm-pre-reloc;
 106         };
 107
 108         sysirq: interrupt-controller@10200a80 {
 109                 compatible = "mediatek,sysirq";
 110                 reg = <0x10200a80 0x20>;
 111                 interrupt-controller;
 112                 #interrupt-cells = <3>;
 113                 interrupt-parent = <&gic>;
 114         };
 115
 116         dramc: dramc@10203000 {
 117                 compatible = "mediatek,mt7629-dramc";
 118                 reg = <0x10203000 0x600>,       /* EMI */
 119                       <0x10213000 0x1000>,      /* DDRPHY */
 120                       <0x10214000 0xd00>;       /* DRAMC_AO */
 121                 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
 122                          <&topckgen CLK_TOP_SYSPLL1_D8>,
 123                          <&topckgen CLK_TOP_MEM_SEL>,
 124                          <&topckgen CLK_TOP_DMPLL>;
 125                 clock-names = "phy", "phy_mux", "mem", "mem_mux";
 126                 u-boot,dm-pre-reloc;
 127         };
 128
 129         apmixedsys: clock-controller@10209000 {
 130                 compatible = "mediatek,mt7629-apmixedsys";
 131                 reg = <0x10209000 0x1000>;
 132                 #clock-cells = <1>;
 133                 u-boot,dm-pre-reloc;
 134         };
 135
 136         topckgen: clock-controller@10210000 {
 137                 compatible = "mediatek,mt7629-topckgen";
 138                 reg = <0x10210000 0x1000>;
 139                 #clock-cells = <1>;
 140                 u-boot,dm-pre-reloc;
 141         };
 142
 143         watchdog: watchdog@10212000 {
 144                 compatible = "mediatek,wdt";
 145                 reg = <0x10212000 0x600>;
 146                 interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>;
 147                 #reset-cells = <1>;
 148                 status = "disabled";
 149         };
 150
 151         wdt-reboot {
 152                 compatible = "wdt-reboot";
 153                 wdt = <&watchdog>;
 154         };
 155
 156         pinctrl: pinctrl@10217000 {
 157                 compatible = "mediatek,mt7629-pinctrl";
 158                 reg = <0x10217000 0x8000>;
 159
 160                 gpio: gpio-controller {
 161                         gpio-controller;
 162                         #gpio-cells = <2>;
 163                 };
 164         };
 165
 166         gic: interrupt-controller@10300000 {
 167                 compatible = "arm,gic-400";
 168                 interrupt-controller;
 169                 #interrupt-cells = <3>;
 170                 interrupt-parent = <&gic>;
 171                 reg = <0x10310000 0x1000>,
 172                       <0x10320000 0x1000>,
 173                       <0x10340000 0x2000>,
 174                       <0x10360000 0x2000>;
 175         };
 176
 177         uart0: serial@11002000 {
 178                 compatible = "mediatek,hsuart";
 179                 reg = <0x11002000 0x400>;
 180                 reg-shift = <2>;
 181                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 182                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 183                          <&pericfg CLK_PERI_UART0_PD>;
 184                 clock-names = "baud", "bus";
 185                 status = "disabled";
 186                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 187                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 188                 u-boot,dm-pre-reloc;
 189         };
 190
 191         uart1: serial@11003000 {
 192                 compatible = "mediatek,hsuart";
 193                 reg = <0x11003000 0x400>;
 194                 reg-shift = <2>;
 195                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 196                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 197                          <&pericfg CLK_PERI_UART1_PD>;
 198                 clock-names = "baud", "bus";
 199                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 200                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 201                 status = "disabled";
 202         };
 203
 204         uart2: serial@11004000 {
 205                 compatible = "mediatek,hsuart";
 206                 reg = <0x11004000 0x400>;
 207                 reg-shift = <2>;
 208                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 209                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 210                          <&pericfg CLK_PERI_UART2_PD>;
 211                 clock-names = "baud", "bus";
 212                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 213                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 214                 status = "disabled";
 215         };
 216
 217         qspi: qspi@11014000 {
 218                 compatible = "mediatek,mt7629-qspi";
 219                 reg = <0x11014000 0xe0>, <0x30000000 0x10000000>;
 220                 reg-names = "reg_base", "mem_base";
 221                 status = "disabled";
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224                 u-boot,dm-pre-reloc;
 225         };
 226
 227         ethsys: syscon@1b000000 {
 228                 compatible = "mediatek,mt7629-ethsys", "syscon";
 229                 reg = <0x1b000000 0x1000>;
 230                 #clock-cells = <1>;
 231         };
 232
 233         sgmiisys0: syscon@1b128000 {
 234                 compatible = "mediatek,mt7629-sgmiisys", "syscon";
 235                 reg = <0x1b128000 0x1000>;
 236                 #clock-cells = <1>;
 237         };
 238
 239         sgmiisys1: syscon@1b130000 {
 240                 compatible = "mediatek,mt7629-sgmiisys", "syscon";
 241                 reg = <0x1b130000 0x1000>;
 242                 #clock-cells = <1>;
 243         };
 244 };