arch/arm/dts/mt7623n-bananapi-bpi-r2.dts

   1 /*
   2  * Copyright (C) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include "mt7623.dtsi"
  10 #include "mt7623-u-boot.dtsi"
  11
  12 / {
  13         model = "Bananapi BPI-R2";
  14         compatible = "bananapi,bpi-r2", "mediatek,mt7623";
  15
  16         chosen {
  17                 stdout-path = &uart2;
  18                 tick-timer = &timer0;
  19         };
  20
  21         reg_1p8v: regulator-1p8v {
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "fixed-1.8V";
  24                 regulator-min-microvolt = <1800000>;
  25                 regulator-max-microvolt = <1800000>;
  26                 regulator-boot-on;
  27                 regulator-always-on;
  28         };
  29
  30         reg_3p3v: regulator-3p3v {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "fixed-3.3V";
  33                 regulator-min-microvolt = <3300000>;
  34                 regulator-max-microvolt = <3300000>;
  35                 regulator-boot-on;
  36                 regulator-always-on;
  37         };
  38
  39         reg_5v: regulator-5v {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "fixed-5V";
  42                 regulator-min-microvolt = <5000000>;
  43                 regulator-max-microvolt = <5000000>;
  44                 regulator-boot-on;
  45                 regulator-always-on;
  46         };
  47
  48         leds {
  49                 compatible = "gpio-leds";
  50
  51                 blue {
  52                         label = "bpi-r2:pio:blue";
  53                         gpios = <&gpio 241 GPIO_ACTIVE_HIGH>;
  54                         default-state = "off";
  55                 };
  56
  57                 green {
  58                         label = "bpi-r2:pio:green";
  59                         gpios = <&gpio 240 GPIO_ACTIVE_HIGH>;
  60                         default-state = "off";
  61                 };
  62
  63                 red {
  64                         label = "bpi-r2:pio:red";
  65                         gpios = <&gpio 239 GPIO_ACTIVE_HIGH>;
  66                         default-state = "off";
  67                 };
  68         };
  69 };
  70
  71 &eth {
  72         status = "okay";
  73         mediatek,gmac-id = <0>;
  74         phy-mode = "rgmii";
  75         mediatek,switch = "mt7530";
  76         reset-gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
  77
  78         fixed-link {
  79                 speed = <1000>;
  80                 full-duplex;
  81         };
  82 };
  83
  84 &mmc0 {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&mmc0_pins_default>;
  87         status = "okay";
  88         bus-width = <8>;
  89         max-frequency = <50000000>;
  90         cap-mmc-highspeed;
  91         vmmc-supply = <&reg_3p3v>;
  92         vqmmc-supply = <&reg_1p8v>;
  93         non-removable;
  94 };
  95
  96 &mmc1 {
  97         pinctrl-names = "default";
  98         pinctrl-0 = <&mmc1_pins_default>;
  99         status = "okay";
 100         bus-width = <4>;
 101         max-frequency = <50000000>;
 102         cap-sd-highspeed;
 103         cd-gpios = <&gpio 261 GPIO_ACTIVE_LOW>;
 104         vmmc-supply = <&reg_3p3v>;
 105         vqmmc-supply = <&reg_3p3v>;
 106 };
 107
 108 &pinctrl {
 109         ephy_default: ephy_default {
 110                 mux {
 111                         function = "eth";
 112                         groups = "mdc_mdio", "ephy";
 113                 };
 114
 115                 conf {
 116                         pins = "G2_TXEN", "G2_TXD0", "G2_TXD1", "G2_TXD2",
 117                                "G2_TXD3", "G2_TXC", "G2_RXC", "G2_RXD0",
 118                                "G2_RXD1", "G2_RXD2", "G2_RXD3", "G2_RXDV",
 119                                "MDC", "MDIO";
 120                         drive-strength = <12>;
 121                         mediatek,tdsel = <5>;
 122                 };
 123         };
 124
 125         mmc0_pins_default: mmc0default {
 126                 mux {
 127                         function = "msdc";
 128                         groups =  "msdc0";
 129                 };
 130
 131                 conf-cmd-data {
 132                         pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
 133                                "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
 134                                "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
 135                         input-enable;
 136                         bias-pull-up;
 137                 };
 138
 139                 conf-clk {
 140                         pins = "MSDC0_CLK";
 141                         bias-pull-down;
 142                 };
 143
 144                 conf-rst {
 145                         pins = "MSDC0_RSTB";
 146                         bias-pull-up;
 147                 };
 148         };
 149
 150         mmc1_pins_default: mmc1default {
 151                 mux {
 152                         function = "msdc";
 153                         groups =  "msdc1", "msdc1_wp_0";
 154                 };
 155
 156                 conf-cmd-data {
 157                         pins = "MSDC1_DAT0", "MSDC1_DAT1", "MSDC1_DAT2",
 158                                "MSDC1_DAT3", "MSDC1_DAT3", "MSDC1_CMD";
 159                         input-enable;
 160                         drive-strength = <4>;
 161                         bias-pull-up;
 162                 };
 163
 164                 conf-clk {
 165                         pins = "MSDC1_CLK";
 166                         drive-strength = <4>;
 167                 };
 168
 169                 conf-wp {
 170                         pins = "EINT7";
 171                         input-enable;
 172                         bias-pull-up;
 173                 };
 174         };
 175
 176         pcie_default: pcie-default {
 177                 mux {
 178                         function = "pcie";
 179                         groups =  "pcie0_0_perst", "pcie1_0_perst";
 180                 };
 181         };
 182
 183         uart0_pins_a: uart0-default {
 184                 mux {
 185                         function = "uart";
 186                         groups =  "uart0_0_txd_rxd";
 187                 };
 188         };
 189
 190         uart1_pins_a: uart1-default {
 191                 mux {
 192                         function = "uart";
 193                         groups =  "uart1_0_txd_rxd";
 194                 };
 195         };
 196
 197         uart2_pins_a: uart2-default {
 198                 mux {
 199                         function = "uart";
 200                         groups =  "uart2_0_txd_rxd";
 201                 };
 202         };
 203
 204         uart2_pins_b: uart2-alt {
 205                 mux {
 206                         function = "uart";
 207                         groups =  "uart2_1_txd_rxd";
 208                 };
 209         };
 210 };
 211
 212 &pcie {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pcie_default>;
 215         status = "okay";
 216
 217         pcie@0,0 {
 218                 status = "okay";
 219         };
 220
 221         pcie@1,0 {
 222                 status = "okay";
 223         };
 224 };
 225
 226 &pcie0_phy {
 227         status = "okay";
 228 };
 229
 230 &pcie1_phy {
 231         status = "okay";
 232 };
 233
 234 &uart0 {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&uart0_pins_a>;
 237         status = "okay";
 238 };
 239
 240 &uart1 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&uart1_pins_a>;
 243         status = "okay";
 244 };
 245
 246 &uart2 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&uart2_pins_a>;
 249         status = "okay";
 250 };