arch/arm/dts/k3-j721e-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721E SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         msmc_ram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x0 0x70000000 0x0 0x800000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x0 0x70000000 0x800000>;
  15
  16                 atf-sram@0 {
  17                         reg = <0x0 0x20000>;
  18                 };
  19         };
  20
  21         gic500: interrupt-controller@1800000 {
  22                 compatible = "arm,gic-v3";
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 ranges;
  26                 #interrupt-cells = <3>;
  27                 interrupt-controller;
  28                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  29                       <0x00 0x01900000 0x00 0x100000>;  /* GICR */
  30
  31                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  32                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  33
  34                 gic_its: gic-its@18200000 {
  35                         compatible = "arm,gic-v3-its";
  36                         reg = <0x00 0x01820000 0x00 0x10000>;
  37                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  38                         msi-controller;
  39                         #msi-cells = <1>;
  40                 };
  41         };
  42
  43         smmu0: smmu@36600000 {
  44                 compatible = "arm,smmu-v3";
  45                 reg = <0x0 0x36600000 0x0 0x100000>;
  46                 interrupt-parent = <&gic500>;
  47                 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
  48                              <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
  49                 interrupt-names = "eventq", "gerror";
  50                 #iommu-cells = <1>;
  51         };
  52
  53         secure_proxy_main: mailbox@32c00000 {
  54                 compatible = "ti,am654-secure-proxy";
  55                 #mbox-cells = <1>;
  56                 reg-names = "target_data", "rt", "scfg";
  57                 reg = <0x00 0x32c00000 0x00 0x100000>,
  58                       <0x00 0x32400000 0x00 0x100000>,
  59                       <0x00 0x32800000 0x00 0x100000>;
  60                 interrupt-names = "rx_011";
  61                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  62         };
  63
  64         main_pmx0: pinmux@11c000 {
  65                 compatible = "pinctrl-single";
  66                 /* Proxy 0 addressing */
  67                 reg = <0x0 0x11c000 0x0 0x2b4>;
  68                 #pinctrl-cells = <1>;
  69                 pinctrl-single,register-width = <32>;
  70                 pinctrl-single,function-mask = <0xffffffff>;
  71         };
  72
  73         main_uart0: serial@2800000 {
  74                 compatible = "ti,j721e-uart", "ti,am654-uart";
  75                 reg = <0x00 0x02800000 0x00 0x100>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <4>;
  78                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  79                 clock-frequency = <48000000>;
  80                 current-speed = <115200>;
  81                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  82                 clocks = <&k3_clks 146 0>;
  83                 clock-names = "fclk";
  84         };
  85
  86         main_uart1: serial@2810000 {
  87                 compatible = "ti,j721e-uart", "ti,am654-uart";
  88                 reg = <0x00 0x02810000 0x00 0x100>;
  89                 reg-shift = <2>;
  90                 reg-io-width = <4>;
  91                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  92                 clock-frequency = <48000000>;
  93                 current-speed = <115200>;
  94                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
  95                 clocks = <&k3_clks 278 0>;
  96                 clock-names = "fclk";
  97         };
  98
  99         main_uart2: serial@2820000 {
 100                 compatible = "ti,j721e-uart", "ti,am654-uart";
 101                 reg = <0x00 0x02820000 0x00 0x100>;
 102                 reg-shift = <2>;
 103                 reg-io-width = <4>;
 104                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 105                 clock-frequency = <48000000>;
 106                 current-speed = <115200>;
 107                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 108                 clocks = <&k3_clks 279 0>;
 109                 clock-names = "fclk";
 110         };
 111
 112         main_uart3: serial@2830000 {
 113                 compatible = "ti,j721e-uart", "ti,am654-uart";
 114                 reg = <0x00 0x02830000 0x00 0x100>;
 115                 reg-shift = <2>;
 116                 reg-io-width = <4>;
 117                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 118                 clock-frequency = <48000000>;
 119                 current-speed = <115200>;
 120                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 121                 clocks = <&k3_clks 280 0>;
 122                 clock-names = "fclk";
 123         };
 124
 125         main_uart4: serial@2840000 {
 126                 compatible = "ti,j721e-uart", "ti,am654-uart";
 127                 reg = <0x00 0x02840000 0x00 0x100>;
 128                 reg-shift = <2>;
 129                 reg-io-width = <4>;
 130                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 131                 clock-frequency = <48000000>;
 132                 current-speed = <115200>;
 133                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 134                 clocks = <&k3_clks 281 0>;
 135                 clock-names = "fclk";
 136         };
 137
 138         main_uart5: serial@2850000 {
 139                 compatible = "ti,j721e-uart", "ti,am654-uart";
 140                 reg = <0x00 0x02850000 0x00 0x100>;
 141                 reg-shift = <2>;
 142                 reg-io-width = <4>;
 143                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 144                 clock-frequency = <48000000>;
 145                 current-speed = <115200>;
 146                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 147                 clocks = <&k3_clks 282 0>;
 148                 clock-names = "fclk";
 149         };
 150
 151         main_uart6: serial@2860000 {
 152                 compatible = "ti,j721e-uart", "ti,am654-uart";
 153                 reg = <0x00 0x02860000 0x00 0x100>;
 154                 reg-shift = <2>;
 155                 reg-io-width = <4>;
 156                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 157                 clock-frequency = <48000000>;
 158                 current-speed = <115200>;
 159                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 160                 clocks = <&k3_clks 283 0>;
 161                 clock-names = "fclk";
 162         };
 163
 164         main_uart7: serial@2870000 {
 165                 compatible = "ti,j721e-uart", "ti,am654-uart";
 166                 reg = <0x00 0x02870000 0x00 0x100>;
 167                 reg-shift = <2>;
 168                 reg-io-width = <4>;
 169                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 170                 clock-frequency = <48000000>;
 171                 current-speed = <115200>;
 172                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 173                 clocks = <&k3_clks 284 0>;
 174                 clock-names = "fclk";
 175         };
 176
 177         main_uart8: serial@2880000 {
 178                 compatible = "ti,j721e-uart", "ti,am654-uart";
 179                 reg = <0x00 0x02880000 0x00 0x100>;
 180                 reg-shift = <2>;
 181                 reg-io-width = <4>;
 182                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 183                 clock-frequency = <48000000>;
 184                 current-speed = <115200>;
 185                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 186                 clocks = <&k3_clks 285 0>;
 187                 clock-names = "fclk";
 188         };
 189
 190         main_uart9: serial@2890000 {
 191                 compatible = "ti,j721e-uart", "ti,am654-uart";
 192                 reg = <0x00 0x02890000 0x00 0x100>;
 193                 reg-shift = <2>;
 194                 reg-io-width = <4>;
 195                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 196                 clock-frequency = <48000000>;
 197                 current-speed = <115200>;
 198                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 199                 clocks = <&k3_clks 286 0>;
 200                 clock-names = "fclk";
 201         };
 202
 203         main_sdhci0: sdhci@4f80000 {
 204                 compatible = "ti,j721e-sdhci-8bit";
 205                 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
 206                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 207                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 208                 clock-names = "clk_xin", "clk_ahb";
 209                 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
 210                 assigned-clocks = <&k3_clks 91 1>;
 211                 assigned-clock-parents = <&k3_clks 91 2>;
 212                 bus-width = <8>;
 213                 ti,otap-del-sel = <0x2>;
 214                 ti,trm-icp = <0x8>;
 215                 dma-coherent;
 216         };
 217
 218         main_sdhci1: sdhci@4fb0000 {
 219                 compatible = "ti,j721e-sdhci-4bit";
 220                 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
 221                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 222                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 223                 clock-names = "clk_xin", "clk_ahb";
 224                 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
 225                 assigned-clocks = <&k3_clks 92 0>;
 226                 assigned-clock-parents = <&k3_clks 92 1>;
 227                 ti,otap-del-sel = <0x2>;
 228                 ti,trm-icp = <0x8>;
 229                 dma-coherent;
 230         };
 231
 232         main_r5fss0: r5fss@5c00000 {
 233                 compatible = "ti,j721e-r5fss";
 234                 lockstep-mode = <0>;
 235                 #address-cells = <1>;
 236                 #size-cells = <1>;
 237                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
 238                          <0x5d00000 0x00 0x5d00000 0x20000>;
 239                 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
 240
 241                 main_r5fss0_core0: r5f@5c00000 {
 242                         compatible = "ti,j721e-r5f";
 243                         reg = <0x5c00000 0x00008000>,
 244                               <0x5c10000 0x00008000>;
 245                         reg-names = "atcm", "btcm";
 246                         ti,sci = <&dmsc>;
 247                         ti,sci-dev-id = <245>;
 248                         ti,sci-proc-ids = <0x06 0xFF>;
 249                         resets = <&k3_reset 245 1>;
 250                         atcm-enable = <1>;
 251                         btcm-enable = <1>;
 252                         loczrama = <1>;
 253                 };
 254
 255                 main_r5fss0_core1: r5f@5d00000 {
 256                         compatible = "ti,j721e-r5f";
 257                         reg = <0x5d00000 0x00008000>,
 258                               <0x5d10000 0x00008000>;
 259                         reg-names = "atcm", "btcm";
 260                         ti,sci = <&dmsc>;
 261                         ti,sci-dev-id = <246>;
 262                         ti,sci-proc-ids = <0x07 0xFF>;
 263                         resets = <&k3_reset 246 1>;
 264                         atcm-enable = <1>;
 265                         btcm-enable = <1>;
 266                         loczrama = <1>;
 267                 };
 268         };
 269
 270         main_r5fss1: r5fss@5e00000 {
 271                 compatible = "ti,j721e-r5fss";
 272                 lockstep-mode = <1>;
 273                 #address-cells = <1>;
 274                 #size-cells = <1>;
 275                 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
 276                          <0x5f00000 0x00 0x5f00000 0x20000>;
 277                 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
 278
 279                 main_r5fss1_core0: r5f@5e00000 {
 280                         compatible = "ti,j721e-r5f";
 281                         reg = <0x5e00000 0x00008000>,
 282                               <0x5e10000 0x00008000>;
 283                         reg-names = "atcm", "btcm";
 284                         ti,sci = <&dmsc>;
 285                         ti,sci-dev-id = <247>;
 286                         ti,sci-proc-ids = <0x08 0xFF>;
 287                         resets = <&k3_reset 247 1>;
 288                         atcm-enable = <1>;
 289                         btcm-enable = <1>;
 290                         loczrama = <1>;
 291                 };
 292
 293                 main_r5fss1_core1: r5f@5f00000 {
 294                         compatible = "ti,j721e-r5f";
 295                         reg = <0x5f00000 0x00008000>,
 296                               <0x5f10000 0x00008000>;
 297                         reg-names = "atcm", "btcm";
 298                         ti,sci = <&dmsc>;
 299                         ti,sci-dev-id = <248>;
 300                         ti,sci-proc-ids = <0x09 0xFF>;
 301                         resets = <&k3_reset 248 1>;
 302                         atcm-enable = <1>;
 303                         btcm-enable = <1>;
 304                         loczrama = <1>;
 305                 };
 306         };
 307
 308         c66_0: dsp@4d80800000 {
 309                 compatible = "ti,j721e-c66-dsp";
 310                 reg = <0x4d 0x80800000 0x00 0x00048000>,
 311                       <0x4d 0x80e00000 0x00 0x00008000>,
 312                       <0x4d 0x80f00000 0x00 0x00008000>;
 313                 reg-names = "l2sram", "l1pram", "l1dram";
 314                 ti,sci = <&dmsc>;
 315                 ti,sci-dev-id = <142>;
 316                 ti,sci-proc-ids = <0x03 0xFF>;
 317                 resets = <&k3_reset 142 1>;
 318         };
 319
 320         c66_1: dsp@4d81800000 {
 321                 compatible = "ti,j721e-c66-dsp";
 322                 reg = <0x4d 0x81800000 0x00 0x00048000>,
 323                       <0x4d 0x81e00000 0x00 0x00008000>,
 324                       <0x4d 0x81f00000 0x00 0x00008000>;
 325                 reg-names = "l2sram", "l1pram", "l1dram";
 326                 ti,sci = <&dmsc>;
 327                 ti,sci-dev-id = <143>;
 328                 ti,sci-proc-ids = <0x04 0xFF>;
 329                 resets = <&k3_reset 143 1>;
 330         };
 331
 332         c71_0: dsp@64800000 {
 333                 compatible = "ti,j721e-c71-dsp";
 334                 reg = <0x00 0x64800000 0x00 0x00080000>,
 335                       <0x00 0x64e00000 0x00 0x0000c000>;
 336                 reg-names = "l2sram", "l1dram";
 337                 ti,sci = <&dmsc>;
 338                 ti,sci-dev-id = <15>;
 339                 ti,sci-proc-ids = <0x30 0xFF>;
 340                 resets = <&k3_reset 15 1>;
 341         };
 342
 343         usbss0: cdns_usb@4104000 {
 344                 compatible = "ti,j721e-usb";
 345                 reg = <0x00 0x4104000 0x00 0x100>;
 346                 dma-coherent;
 347                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
 348                 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
 349                 clock-names = "usb2_refclk", "lpm_clk";
 350                 assigned-clocks = <&k3_clks 288 15>;    /* USB2_REFCLK */
 351                 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
 352                 #address-cells = <2>;
 353                 #size-cells = <2>;
 354                 ranges;
 355
 356                 phy@4108000 {
 357                         compatible = "ti,j721e-usb2-phy";
 358                         reg = <0x00 0x4108000 0x00 0x400>;
 359                 };
 360
 361                 usb0: usb@6000000 {
 362                         compatible = "cdns,usb3";
 363                         reg = <0x00 0x6000000 0x00 0x10000>,
 364                               <0x00 0x6010000 0x00 0x10000>,
 365                               <0x00 0x6020000 0x00 0x10000>;
 366                         reg-names = "otg", "xhci", "dev";
 367                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
 368                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 369                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 370                         interrupt-names = "host",
 371                                           "peripheral",
 372                                           "otg";
 373                         maximum-speed = "super-speed";
 374                         dr_mode = "otg";
 375                 };
 376         };
 377
 378         usbss1: cdns_usb@4114000 {
 379                 compatible = "ti,j721e-usb";
 380                 reg = <0x00 0x4114000 0x00 0x100>;
 381                 dma-coherent;
 382                 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
 383                 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
 384                 clock-names = "usb2_refclk", "lpm_clk";
 385                 assigned-clocks = <&k3_clks 289 15>;    /* USB2_REFCLK */
 386                 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
 387                 #address-cells = <2>;
 388                 #size-cells = <2>;
 389                 ranges;
 390
 391                 phy@4118000 {
 392                         compatible = "ti,j721e-usb2-phy";
 393                         reg = <0x00 0x4118000 0x00 0x400>;
 394                 };
 395
 396                 usb1: usb@6400000 {
 397                         compatible = "cdns,usb3";
 398                         reg = <0x00 0x6400000 0x00 0x10000>,
 399                               <0x00 0x6410000 0x00 0x10000>,
 400                               <0x00 0x6420000 0x00 0x10000>;
 401                         reg-names = "otg", "xhci", "dev";
 402                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 403                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 404                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 405                         interrupt-names = "host",
 406                                           "peripheral",
 407                                           "otg";
 408                         maximum-speed = "super-speed";
 409                         dr_mode = "otg";
 410                 };
 411         };
 412
 413         ufs_wrapper: ufs-wrapper@4e80000 {
 414                 compatible = "ti,j721e-ufs";
 415                 reg = <0x0 0x4e80000 0x0 0x100>;
 416                 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
 417                 clocks = <&k3_clks 277 1>;
 418                 assigned-clocks = <&k3_clks 277 1>;
 419                 assigned-clock-parents = <&k3_clks 277 4>;
 420                 ranges;
 421                 #address-cells = <2>;
 422                 #size-cells = <2>;
 423
 424                 ufs@4e84000 {
 425                         compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
 426                         reg = <0x0 0x4e84000 0x0 0x10000>;
 427                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 428                         freq-table-hz = <0 0>, <0 0>;
 429                         clocks = <&k3_clks 277 0>, <&k3_clks 277 1>;
 430                         clock-names = "core_clk", "phy_clk";
 431                         assigned-clocks = <&k3_clks 277 1>;
 432                         assigned-clock-parents = <&k3_clks 277 4>;
 433                         dma-coherent;
 434                 };
 435         };
 436
 437         main_i2c0: i2c@2000000 {
 438                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 439                 reg = <0x0 0x2000000 0x0 0x100>;
 440                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 clock-names = "fck";
 444                 clocks = <&k3_clks 187 0>;
 445                 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
 446         };
 447
 448         main_i2c1: i2c@2010000 {
 449                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 450                 reg = <0x0 0x2010000 0x0 0x100>;
 451                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 452                 #address-cells = <1>;
 453                 #size-cells = <0>;
 454                 clock-names = "fck";
 455                 clocks = <&k3_clks 188 0>;
 456                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 457         };
 458
 459         main_i2c2: i2c@2020000 {
 460                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 461                 reg = <0x0 0x2020000 0x0 0x100>;
 462                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 clock-names = "fck";
 466                 clocks = <&k3_clks 189 0>;
 467                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 468         };
 469
 470         main_i2c3: i2c@2030000 {
 471                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 472                 reg = <0x0 0x2030000 0x0 0x100>;
 473                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 clock-names = "fck";
 477                 clocks = <&k3_clks 190 0>;
 478                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 479         };
 480
 481         main_i2c4: i2c@2040000 {
 482                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 483                 reg = <0x0 0x2040000 0x0 0x100>;
 484                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 clock-names = "fck";
 488                 clocks = <&k3_clks 191 0>;
 489                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 490         };
 491
 492         main_i2c5: i2c@2050000 {
 493                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 494                 reg = <0x0 0x2050000 0x0 0x100>;
 495                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 clock-names = "fck";
 499                 clocks = <&k3_clks 192 0>;
 500                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 501         };
 502
 503         main_i2c6: i2c@2060000 {
 504                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 505                 reg = <0x0 0x2060000 0x0 0x100>;
 506                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 clock-names = "fck";
 510                 clocks = <&k3_clks 193 0>;
 511                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
 512         };
 513 };