arch/arm/dts/imxrt1050.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2019
   4  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
   5  */
   6
   7 #include "skeleton.dtsi"
   8 #include "armv7-m.dtsi"
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/imxrt1050-clock.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/memory/imxrt-sdram.h>
  13
  14 / {
  15         aliases {
  16                 gpio0 = &gpio1;
  17                 gpio1 = &gpio2;
  18                 gpio2 = &gpio3;
  19                 gpio3 = &gpio4;
  20                 gpio4 = &gpio5;
  21                 mmc0 = &usdhc1;
  22                 serial0 = &lpuart1;
  23         };
  24
  25         clocks {
  26                 u-boot,dm-spl;
  27
  28                 osc {
  29                         u-boot,dm-spl;
  30                         compatible = "fsl,imx-osc", "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <24000000>;
  33                 };
  34         };
  35
  36         soc {
  37                 u-boot,dm-spl;
  38
  39                 semc: semc@402f0000 {
  40                         u-boot,dm-spl;
  41                         compatible = "fsl,imxrt-semc";
  42                         reg = <0x402f0000 0x4000>;
  43                         clocks = <&clks IMXRT1050_CLK_SEMC>;
  44                         pinctrl-0 = <&pinctrl_semc>;
  45                         pinctrl-names = "default";
  46                         status = "okay";
  47                 };
  48
  49                 lpuart1: serial@40184000 {
  50                         compatible = "fsl,imxrt-lpuart";
  51                         reg = <0x40184000 0x4000>;
  52                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  53                         clocks = <&clks IMXRT1050_CLK_LPUART1>;
  54                         clock-names = "per";
  55                         status = "disabled";
  56                 };
  57
  58                 iomuxc: iomuxc@401f8000 {
  59                         compatible = "fsl,imxrt-iomuxc";
  60                         reg = <0x401f8000 0x4000>;
  61                         fsl,mux_mask = <0x7>;
  62                 };
  63
  64                 clks: ccm@400fc000 {
  65                         u-boot,dm-spl;
  66                         compatible = "fsl,imxrt1050-ccm";
  67                         reg = <0x400fc000 0x4000>;
  68                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  70                         #clock-cells = <1>;
  71                 };
  72
  73                 usdhc1: usdhc@402c0000 {
  74                         u-boot,dm-spl;
  75                         compatible = "fsl,imxrt-usdhc";
  76                         reg = <0x402c0000 0x10000>;
  77                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  78                         clocks = <&clks IMXRT1050_CLK_USDHC1>;
  79                         clock-names = "per";
  80                         bus-width = <4>;
  81                         fsl,tuning-start-tap = <20>;
  82                         fsl,tuning-step= <2>;
  83                         status = "disabled";
  84                 };
  85
  86                 gpio1: gpio@401b8000 {
  87                         u-boot,dm-spl;
  88                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  89                         reg = <0x401b8000 0x4000>;
  90                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  92                         gpio-controller;
  93                         #gpio-cells = <2>;
  94                         interrupt-controller;
  95                         #interrupt-cells = <2>;
  96                 };
  97
  98                 gpio2: gpio@401bc000 {
  99                         u-boot,dm-spl;
 100                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 101                         reg = <0x401bc000 0x4000>;
 102                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 103                                 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 104                         gpio-controller;
 105                         #gpio-cells = <2>;
 106                         interrupt-controller;
 107                         #interrupt-cells = <2>;
 108                 };
 109
 110                 gpio3: gpio@401c0000 {
 111                         u-boot,dm-spl;
 112                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 113                         reg = <0x401c0000 0x4000>;
 114                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 115                                 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 116                         gpio-controller;
 117                         #gpio-cells = <2>;
 118                         interrupt-controller;
 119                         #interrupt-cells = <2>;
 120                 };
 121
 122                 gpio4: gpio@401c4000 {
 123                         u-boot,dm-spl;
 124                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 125                         reg = <0x401c4000 0x4000>;
 126                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 127                                         <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 128                         gpio-controller;
 129                         #gpio-cells = <2>;
 130                         interrupt-controller;
 131                         #interrupt-cells = <2>;
 132                 };
 133
 134                 gpio5: gpio@400c0000 {
 135                         u-boot,dm-spl;
 136                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 137                         reg = <0x400c0000 0x4000>;
 138                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 139                                 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 140                         gpio-controller;
 141                         #gpio-cells = <2>;
 142                         interrupt-controller;
 143                         #interrupt-cells = <2>;
 144                 };
 145         };
 146 };