arch/arm/dts/imxrt1050.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2019
   4  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
   5  */
   6
   7 #include "skeleton.dtsi"
   8 #include "armv7-m.dtsi"
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/imxrt1050-clock.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/memory/imxrt-sdram.h>
  13
  14 / {
  15         aliases {
  16                 display0 = &lcdif;
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 mmc0 = &usdhc1;
  23                 serial0 = &lpuart1;
  24         };
  25
  26         clocks {
  27                 u-boot,dm-spl;
  28
  29                 osc {
  30                         u-boot,dm-spl;
  31                         compatible = "fsl,imx-osc", "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <24000000>;
  34                 };
  35         };
  36
  37         soc {
  38                 u-boot,dm-spl;
  39
  40                 semc: semc@402f0000 {
  41                         u-boot,dm-spl;
  42                         compatible = "fsl,imxrt-semc";
  43                         reg = <0x402f0000 0x4000>;
  44                         clocks = <&clks IMXRT1050_CLK_SEMC>;
  45                         pinctrl-0 = <&pinctrl_semc>;
  46                         pinctrl-names = "default";
  47                         status = "okay";
  48                 };
  49
  50                 lpuart1: serial@40184000 {
  51                         compatible = "fsl,imxrt-lpuart";
  52                         reg = <0x40184000 0x4000>;
  53                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&clks IMXRT1050_CLK_LPUART1>;
  55                         clock-names = "per";
  56                         status = "disabled";
  57                 };
  58
  59                 iomuxc: iomuxc@401f8000 {
  60                         compatible = "fsl,imxrt-iomuxc";
  61                         reg = <0x401f8000 0x4000>;
  62                         fsl,mux_mask = <0x7>;
  63                 };
  64
  65                 clks: ccm@400fc000 {
  66                         u-boot,dm-spl;
  67                         compatible = "fsl,imxrt1050-ccm";
  68                         reg = <0x400fc000 0x4000>;
  69                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  71                         #clock-cells = <1>;
  72                 };
  73
  74                 usdhc1: usdhc@402c0000 {
  75                         u-boot,dm-spl;
  76                         compatible = "fsl,imxrt-usdhc";
  77                         reg = <0x402c0000 0x10000>;
  78                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  79                         clocks = <&clks IMXRT1050_CLK_USDHC1>;
  80                         clock-names = "per";
  81                         bus-width = <4>;
  82                         fsl,tuning-start-tap = <20>;
  83                         fsl,tuning-step= <2>;
  84                         status = "disabled";
  85                 };
  86
  87                 gpio1: gpio@401b8000 {
  88                         u-boot,dm-spl;
  89                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  90                         reg = <0x401b8000 0x4000>;
  91                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  93                         gpio-controller;
  94                         #gpio-cells = <2>;
  95                         interrupt-controller;
  96                         #interrupt-cells = <2>;
  97                 };
  98
  99                 gpio2: gpio@401bc000 {
 100                         u-boot,dm-spl;
 101                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 102                         reg = <0x401bc000 0x4000>;
 103                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 104                                 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 105                         gpio-controller;
 106                         #gpio-cells = <2>;
 107                         interrupt-controller;
 108                         #interrupt-cells = <2>;
 109                 };
 110
 111                 gpio3: gpio@401c0000 {
 112                         u-boot,dm-spl;
 113                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 114                         reg = <0x401c0000 0x4000>;
 115                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 116                                 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 117                         gpio-controller;
 118                         #gpio-cells = <2>;
 119                         interrupt-controller;
 120                         #interrupt-cells = <2>;
 121                 };
 122
 123                 gpio4: gpio@401c4000 {
 124                         u-boot,dm-spl;
 125                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 126                         reg = <0x401c4000 0x4000>;
 127                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 128                                         <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 129                         gpio-controller;
 130                         #gpio-cells = <2>;
 131                         interrupt-controller;
 132                         #interrupt-cells = <2>;
 133                 };
 134
 135                 gpio5: gpio@400c0000 {
 136                         u-boot,dm-spl;
 137                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 138                         reg = <0x400c0000 0x4000>;
 139                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 140                                 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 141                         gpio-controller;
 142                         #gpio-cells = <2>;
 143                         interrupt-controller;
 144                         #interrupt-cells = <2>;
 145                 };
 146
 147                 lcdif: lcdif@402b8000 {
 148                     compatible = "fsl,imxrt-lcdif";
 149                     reg = <0x402b8000 0x10000>;
 150                     interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 151                     clocks = <&clks IMXRT1050_CLK_LCDIF>;
 152                     clock-names = "per";
 153                     status = "disabled";
 154                 };
 155         };
 156 };