arch/arm/dts/imx7-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2016-2019 Toradex AG
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include "imx7d.dtsi"
   9
  10 &i2c1 {
  11         pinctrl-names = "default", "gpio";
  12         pinctrl-0 = <&pinctrl_i2c1>;
  13         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  14         sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  15         scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  16         status = "okay";
  17
  18         rn5t567@33 {
  19                 compatible = "ricoh,rn5t567";
  20                 reg = <0x33>;
  21         };
  22 };
  23
  24 &i2c4 {
  25         pinctrl-names = "default", "gpio";
  26         pinctrl-0 = <&pinctrl_i2c4>;
  27         pinctrl-1 = <&pinctrl_i2c4_gpio>;
  28         sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
  29         scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
  30         status = "okay";
  31 };
  32
  33 &uart1 {
  34         pinctrl-names = "default";
  35         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
  36         uart-has-rtscts;
  37         fsl,dte-mode;
  38         status = "okay";
  39 };
  40
  41 &usdhc1 {
  42         pinctrl-names = "default";
  43         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
  44         no-1-8-v;
  45         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
  46         disable-wp;
  47         status = "okay";
  48 };
  49
  50 &iomuxc {
  51         pinctrl_i2c4: i2c4-grp {
  52                 fsl,pins = <
  53                         MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA      0x4000007f
  54                         MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL      0x4000007f
  55                 >;
  56         };
  57
  58         pinctrl_i2c4_gpio: i2c4-gpio-grp {
  59                         fsl,pins = <
  60                         MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9     0x4000007f
  61                         MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8     0x4000007f
  62                 >;
  63         };
  64
  65         pinctrl_uart1: uart1-grp {
  66                 fsl,pins = <
  67                         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX    0x79
  68                         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX    0x79
  69                         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS    0x79
  70                         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS    0x79
  71                 >;
  72         };
  73
  74         pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
  75                 fsl,pins = <
  76                         MX7D_PAD_SD2_DATA1__GPIO5_IO15          0x14 /* DCD */
  77                         MX7D_PAD_SD2_DATA0__GPIO5_IO14          0x14 /* DTR */
  78                 >;
  79         };
  80
  81         pinctrl_usdhc1: usdhc1-grp {
  82                 fsl,pins = <
  83                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
  84                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
  85                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
  86                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
  87                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
  88                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
  89                 >;
  90         };
  91 };
  92
  93 &iomuxc_lpsr {
  94         pinctrl_i2c1: i2c1-grp {
  95                 fsl,pins = <
  96                         MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA      0x4000007f
  97                         MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL      0x4000007f
  98                 >;
  99         };
 100
 101         pinctrl_i2c1_gpio: i2c1-gpio-grp {
 102                 fsl,pins = <
 103                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x4000007f
 104                         MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4     0x4000007f
 105                 >;
 106         };
 107
 108         pinctrl_cd_usdhc1: usdhc1-cd-grp {
 109                 fsl,pins = <
 110                         MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0     0x59 /* CD */
 111                 >;
 112         };
 113 };
 114
 115 &lcdif {
 116         u-boot,dm-pre-reloc;
 117         status = "okay";
 118
 119         display-timings {
 120                 native-mode = <&timing_vga>;
 121
 122                 /* Standard VGA timing */
 123                 timing_vga: 640x480 {
 124                         u-boot,dm-pre-reloc;
 125                         clock-frequency = <25175000>;
 126                         hactive = <640>;
 127                         vactive = <480>;
 128                         hback-porch = <48>;
 129                         hfront-porch = <16>;
 130                         vback-porch = <33>;
 131                         vfront-porch = <10>;
 132                         hsync-len = <96>;
 133                         vsync-len = <2>;
 134
 135                         de-active = <1>;
 136                         hsync-active = <0>;
 137                         vsync-active = <0>;
 138                         pixelclk-active = <0>;
 139                 };
 140         };
 141 };