arch/arm/dts/imx6ull-dart-6ul.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
   4  */
   5
   6 / {
   7         model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
   8         compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
   9
  10         memory {
  11                 reg = <0x80000000 0x20000000>;
  12         };
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17 };
  18
  19 &fec1 {
  20         pinctrl-names = "default";
  21         pinctrl-0 = <&pinctrl_enet1>;
  22         phy-mode = "rmii";
  23         phy-handle = <&ethphy0>;
  24         status = "okay";
  25
  26         mdio1: mdio1 {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 ethphy0: ethernet-phy@1 {
  31                         reg = <1>;
  32                         micrel,led-mode = <1>;
  33                 };
  34         };
  35 };
  36
  37 &fec2 {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_enet2>;
  40         phy-mode = "rmii";
  41         phy-handle = <&ethphy1>;
  42         status = "okay";
  43
  44         mdio2: mdio2 {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 ethphy1: ethernet-phy@2 {
  49                         reg = <2>;
  50                         micrel,led-mode = <1>;
  51                 };
  52         };
  53 };
  54
  55 &gpmi {
  56         pinctrl-names = "default";
  57         pinctrl-0 = <&pinctrl_gpmi_nand>;
  58         nand-on-flash-bbt;
  59         fsl,no-blockmark-swap;
  60         status = "disabled";
  61
  62         #address-cells = <1>;
  63         #size-cells = <1>;
  64
  65         partition@0 {
  66                 label = "uboot";
  67                 reg = <0x0 0x400000>;
  68         };
  69
  70         partition@400000 {
  71                 label = "uboot-env";
  72                 reg = <0x400000 0x100000>;
  73         };
  74
  75         partition@500000 {
  76                 label = "root";
  77                 reg = <0x500000 0x0>;
  78         };
  79 };
  80
  81 &i2c1 {
  82         clock-frequency = <100000>;
  83         pinctrl-names = "default", "gpio";
  84         pinctrl-0 = <&pinctrl_i2c1>;
  85         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  86         scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  87         sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  88         status = "okay";
  89 };
  90
  91 &i2c2 {
  92         clock-frequency = <100000>;
  93         pinctrl-names = "default", "gpio";
  94         pinctrl-0 = <&pinctrl_i2c2>;
  95         pinctrl-1 = <&pinctrl_i2c2_gpio>;
  96         scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
  97         sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
  98         status = "okay";
  99
 100         eeprom@50 {
 101                 compatible = "cat,24c32";
 102                 reg = <0x50>;
 103         };
 104 };
 105
 106 &pwm1 {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_pwm1>;
 109         #pwm-cells = <3>;
 110         status = "okay";
 111 };
 112
 113 &uart1 {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&pinctrl_uart1>;
 116         status = "okay";
 117 };
 118
 119 &usdhc1 {
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&pinctrl_usdhc1>;
 122         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 123         bus-width = <0x4>;
 124         no-1-8-v;
 125         status = "okay";
 126 };
 127
 128 &usdhc2 {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_usdhc2>;
 131         bus-width = <8>;
 132         no-1-8-v;
 133         non-removable;
 134         keep-power-in-suspend;
 135         status = "disabled";
 136 };
 137
 138 &iomuxc {
 139         pinctrl-names = "default";
 140
 141         pinctrl_enet1: enet1grp {
 142                 fsl,pins = <
 143                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 144                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0X1b0b0
 145                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 146                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 147                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 148                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 149                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 150                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 151                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 152                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 153                 >;
 154         };
 155
 156         pinctrl_enet2: enet2grp {
 157                 fsl,pins = <
 158                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 159                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0X1b0b0
 160                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 161                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 162                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 163                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 164                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 165                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 166                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 167                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 168                 >;
 169         };
 170
 171         pinctrl_gpmi_nand: gpminandgrp {
 172                 fsl,pins = <
 173                         MX6UL_PAD_NAND_DQS__RAWNAND_DQS         0x0b0b1
 174                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 175                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 176                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 177                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 178                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 179                         MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0x0b0b1
 180                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 181                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 182                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 183                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 184                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 185                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 186                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 187                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 188                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 189                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 190                 >;
 191         };
 192
 193         pinctrl_i2c1: i2cgrp {
 194                 fsl,pins = <
 195                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
 196                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
 197                 >;
 198         };
 199
 200         pinctrl_i2c1_gpio: i2c1grp_gpio {
 201                 fsl,pins = <
 202                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
 203                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
 204                 >;
 205         };
 206
 207         pinctrl_i2c2: i2cgrp {
 208                 fsl,pins = <
 209                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
 210                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
 211                 >;
 212         };
 213
 214         pinctrl_i2c2_gpio: i2c2grp_gpio {
 215                 fsl,pins = <
 216                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x1b8b0
 217                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x1b8b0
 218                 >;
 219         };
 220
 221         pinctrl_pwm1: pwm1grp {
 222                 fsl,pins = <
 223                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x1b0b1
 224                 >;
 225         };
 226
 227         pinctrl_uart1: uart1grp {
 228                 fsl,pins = <
 229                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
 230                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
 231                 >;
 232         };
 233
 234         pinctrl_usdhc1: usdhc1grp {
 235                 fsl,pins = <
 236                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 237                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 238                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 239                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 240                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 241                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 242                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
 243
 244                 >;
 245         };
 246
 247         pinctrl_usdhc2: usdhc2grp {
 248                 fsl,pins = <
 249                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9
 250                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
 251                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170f9
 252                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170f9
 253                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170f9
 254                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170f9
 255                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x170f9
 256                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x170f9
 257                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x170f9
 258                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x170f9
 259                 >;
 260         };
 261 };