arch/arm/dts/imx6ul-phytec-phycore-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   4  * Author: Christian Hemp <c.hemp@phytec.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/pwm/pwm.h>
  10
  11 / {
  12         model = "PHYTEC phyCORE-i.MX6 UltraLite";
  13         compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x20000000>;
  22         };
  23
  24         gpio_leds_som: leds {
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_gpioleds_som>;
  27                 compatible = "gpio-leds";
  28
  29                 phycore-green {
  30                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  31                         linux,default-trigger = "heartbeat";
  32                 };
  33         };
  34 };
  35
  36 &fec1 {
  37         pinctrl-names = "default";
  38         pinctrl-0 = <&pinctrl_enet1>;
  39         phy-mode = "rmii";
  40         phy-handle = <&ethphy1>;
  41         status = "disabled";
  42
  43         mdio: mdio {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 ethphy1: ethernet-phy@1 {
  48                         reg = <1>;
  49                         interrupt-parent = <&gpio1>;
  50                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
  51                         micrel,led-mode = <1>;
  52                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
  53                         clock-names = "rmii-ref";
  54                         status = "disabled";
  55                 };
  56         };
  57 };
  58
  59 &gpmi {
  60         pinctrl-names = "default";
  61         pinctrl-0 = <&pinctrl_gpmi_nand>;
  62         nand-on-flash-bbt;
  63         status = "disabled";
  64 };
  65
  66 &i2c1 {
  67         pinctrl-names = "default";
  68         pinctrl-0 = <&pinctrl_i2c1>;
  69         clock-frequency = <100000>;
  70         status = "okay";
  71
  72         eeprom@52 {
  73                 compatible = "catalyst,24c32", "atmel,24c32";
  74                 reg = <0x52>;
  75         };
  76 };
  77
  78 &snvs_poweroff {
  79         status = "okay";
  80 };
  81
  82 &uart1 {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_uart1>;
  85         status = "okay";
  86 };
  87
  88 &usdhc2 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_usdhc2>;
  91         bus-width = <8>;
  92         no-1-8-v;
  93         non-removable;
  94         status = "disabled";
  95 };
  96
  97 &iomuxc {
  98         pinctrl_enet1: enet1grp {
  99                 fsl,pins = <
 100                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x10010
 101                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x10010
 102                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 103                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 104                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 105                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 106                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b010
 107                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
 108                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
 109                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b010
 110                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x17059
 111                 >;
 112         };
 113
 114         pinctrl_gpioleds_som: gpioledssomgrp {
 115                 fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04  0x0b0b0>;
 116         };
 117
 118         pinctrl_gpmi_nand: gpminandgrp {
 119                 fsl,pins = <
 120                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 121                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 122                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 123                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 124                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 125                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 126                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 127                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 128                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 129                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 130                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 131                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 132                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 133                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 134                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 135                 >;
 136         };
 137
 138         pinctrl_i2c1: i2cgrp {
 139                 fsl,pins = <
 140                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
 141                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
 142                 >;
 143         };
 144
 145         pinctrl_uart1: uart1grp {
 146                 fsl,pins = <
 147                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
 148                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
 149                 >;
 150         };
 151
 152         pinctrl_usdhc2: usdhc2grp {
 153                 fsl,pins = <
 154                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9
 155                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
 156                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170f9
 157                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170f9
 158                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170f9
 159                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170f9
 160                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x170f9
 161                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x170f9
 162                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x170f9
 163                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x170f9
 164                 >;
 165         };
 166
 167 };