arch/arm/dts/imx6q-display5.dts

   1 /*
   2  * Copyright 2017
   3  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 /dts-v1/;
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include "imx6q.dtsi"
  15
  16 / {
  17         model = "Liebherr (LWN) display5 i.MX6 Quad Board";
  18         compatible = "lwn,display5", "fsl,imx6q";
  19
  20         memory@10000000 {
  21                 device_type = "memory";
  22                 reg = <0x10000000 0x40000000>;
  23         };
  24 };
  25
  26 &ecspi2 {
  27         cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
  28         pinctrl-names = "default";
  29         pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>;
  30         status = "okay";
  31
  32         s25fl256s: flash@0 {
  33                 #address-cells = <1>;
  34                 #size-cells = <1>;
  35                 compatible = "jedec,spi-nor";
  36                 spi-max-frequency = <40000000>;
  37                 reg = <0>;
  38
  39                 partition@0 {
  40                         label = "SPL (spi)";
  41                         reg = <0x0 0x20000>;
  42                         read-only;
  43                 };
  44                 partition@1 {
  45                         label = "u-boot (spi)";
  46                         reg = <0x20000 0x100000>;
  47                         read-only;
  48                 };
  49                 partition@2 {
  50                         label = "uboot-env (spi)";
  51                         reg = <0x120000 0x10000>;
  52                 };
  53                 partition@3 {
  54                         label = "uboot-envr (spi)";
  55                         reg = <0x130000 0x10000>;
  56                 };
  57                 partition@4 {
  58                         label = "linux-recovery (spi)";
  59                         reg = <0x140000 0x800000>;
  60                 };
  61                 partition@5 {
  62                         label = "swupdate-fitImg (spi)";
  63                         reg = <0x940000 0x400000>;
  64                 };
  65                 partition@6 {
  66                         label = "swupdate-initramfs (spi)";
  67                         reg = <0xD40000 0x800000>;
  68                 };
  69         };
  70 };
  71
  72 &ecspi3 {
  73         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  74         pinctrl-names = "default";
  75         pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
  76         status = "okay";
  77 };
  78
  79 &fec {
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_enet>;
  82         phy-handle = <&ethernet_phy0>;
  83         phy-mode = "rgmii-id";
  84         status = "okay";
  85
  86         mdio {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 ethernet_phy0: ethernet-phy@0 {
  90                         compatible = "marvell,88E1510";
  91                         device_type = "ethernet-phy";
  92                         /* Set LED0 control: */
  93                         /* On - Link, Blink - Activity, Off - No Link */
  94                         marvell,reg-init = <3 0x10 0 0x1011>;
  95                         max-speed = <100>;
  96                         reg = <0>;
  97                 };
  98         };
  99 };
 100
 101 &i2c1 {
 102         clock-frequency = <400000>;
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_i2c1>;
 105         status = "okay";
 106
 107         codec: tfa9879@6c {
 108                 #sound-dai-cells = <0>;
 109                 compatible = "nxp,tfa9879";
 110                 reg = <0x6C>;
 111         };
 112 };
 113
 114 &i2c2 {
 115         clock-frequency = <400000>;
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_i2c2>;
 118         status = "okay";
 119 };
 120
 121 &i2c3 {
 122         clock-frequency = <400000>;
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&pinctrl_i2c3>;
 125         status = "okay";
 126
 127         at24@50 {
 128                 compatible = "atmel,24c256";
 129                 pagesize = <64>;
 130                 reg = <0x50>;
 131         };
 132
 133         pfuze100: pmic@8 {
 134                 compatible = "fsl,pfuze100";
 135                 reg = <0x08>;
 136
 137                 regulators {
 138                         sw1a_reg: sw1ab {
 139                                 regulator-min-microvolt = <300000>;
 140                                 regulator-max-microvolt = <1875000>;
 141                                 regulator-boot-on;
 142                                 regulator-always-on;
 143                                 regulator-ramp-delay = <6250>;
 144                         };
 145
 146                         sw1c_reg: sw1c {
 147                                 regulator-min-microvolt = <300000>;
 148                                 regulator-max-microvolt = <1875000>;
 149                                 regulator-boot-on;
 150                                 regulator-always-on;
 151                                 regulator-ramp-delay = <6250>;
 152                         };
 153
 154                         sw2_reg: sw2 {
 155                                 regulator-min-microvolt = <800000>;
 156                                 regulator-max-microvolt = <3950000>;
 157                                 regulator-boot-on;
 158                                 regulator-always-on;
 159                         };
 160
 161                         sw3a_reg: sw3a {
 162                                 regulator-min-microvolt = <400000>;
 163                                 regulator-max-microvolt = <1975000>;
 164                                 regulator-boot-on;
 165                                 regulator-always-on;
 166                         };
 167
 168                         sw3b_reg: sw3b {
 169                                 regulator-min-microvolt = <400000>;
 170                                 regulator-max-microvolt = <1975000>;
 171                                 regulator-boot-on;
 172                                 regulator-always-on;
 173                         };
 174
 175                         sw4_reg: sw4 {
 176                                 regulator-min-microvolt = <800000>;
 177                                 regulator-max-microvolt = <3300000>;
 178                         };
 179
 180                         swbst_reg: swbst {
 181                                 regulator-min-microvolt = <5000000>;
 182                                 regulator-max-microvolt = <5150000>;
 183                         };
 184
 185                         snvs_reg: vsnvs {
 186                                 regulator-min-microvolt = <1000000>;
 187                                 regulator-max-microvolt = <3000000>;
 188                                 regulator-boot-on;
 189                                 regulator-always-on;
 190                         };
 191
 192                         vref_reg: vrefddr {
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                         };
 196
 197                         vgen1_reg: vgen1 {
 198                                 regulator-min-microvolt = <800000>;
 199                                 regulator-max-microvolt = <1550000>;
 200                         };
 201
 202                         vgen2_reg: vgen2 {
 203                                 regulator-min-microvolt = <800000>;
 204                                 regulator-max-microvolt = <1550000>;
 205                         };
 206
 207                         vgen3_reg: vgen3 {
 208                                 regulator-min-microvolt = <1800000>;
 209                                 regulator-max-microvolt = <3300000>;
 210                         };
 211
 212                         vgen4_reg: vgen4 {
 213                                 regulator-min-microvolt = <1800000>;
 214                                 regulator-max-microvolt = <3300000>;
 215                                 regulator-always-on;
 216                         };
 217
 218                         vgen5_reg: vgen5 {
 219                                 regulator-min-microvolt = <1800000>;
 220                                 regulator-max-microvolt = <3300000>;
 221                                 regulator-always-on;
 222                         };
 223
 224                         vgen6_reg: vgen6 {
 225                                 regulator-min-microvolt = <1800000>;
 226                                 regulator-max-microvolt = <3300000>;
 227                                 regulator-always-on;
 228                         };
 229                 };
 230         };
 231 };
 232
 233 &uart4 {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_uart4>;
 236         uart-has-rtscts;
 237         status = "okay";
 238 };
 239
 240 &uart5 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_uart5>;
 243         status = "okay";
 244 };
 245
 246 &usdhc4 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_usdhc4>;
 249         bus-width = <8>;
 250         non-removable;
 251         status = "okay";
 252 };
 253
 254 &iomuxc {
 255         pinctrl_ecspi2: ecspi2grp {
 256                 fsl,pins = <
 257                         MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO      0x100b1
 258                         MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI       0x100b1
 259                         MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK       0x100b1
 260                 >;
 261         };
 262
 263         pinctrl_ecspi2_cs: ecspi2csgrp {
 264                 fsl,pins = <
 265                         MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
 266                 >;
 267         };
 268
 269         pinctrl_ecspi2_flwp: ecspi2flwpgrp {
 270                 fsl,pins = <
 271                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
 272                 >;
 273         };
 274
 275         pinctrl_ecspi3: ecspi3grp {
 276                 fsl,pins = <
 277                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 278                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 279                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 280                 >;
 281         };
 282
 283         pinctrl_ecspi3_cs: ecspi3csgrp {
 284                 fsl,pins = <
 285                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
 286                 >;
 287         };
 288
 289         pinctrl_ecspi3_flwp: ecspi3flwpgrp {
 290                 fsl,pins = <
 291                         MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
 292                 >;
 293         };
 294
 295         pinctrl_enet: enetgrp {
 296                 fsl,pins = <
 297                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 298                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 299                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 300                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 301                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 302                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 303                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 304                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 305                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 306                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 307                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 308                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 309                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 310                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 311                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 312                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
 313                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 314                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
 315                 >;
 316         };
 317
 318         pinctrl_i2c1: i2c1grp {
 319                 fsl,pins = <
 320                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
 321                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
 322                 >;
 323         };
 324
 325         pinctrl_i2c2: i2c2grp {
 326                 fsl,pins = <
 327                         MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 328                         MX6QDL_PAD_EIM_D16__I2C2_SDA    0x4001b8b1
 329                 >;
 330         };
 331
 332         pinctrl_i2c3: i2c3grp {
 333                 fsl,pins = <
 334                         MX6QDL_PAD_EIM_D17__I2C3_SCL    0x4001b8b1
 335                         MX6QDL_PAD_EIM_D18__I2C3_SDA    0x4001b8b1
 336                 >;
 337         };
 338
 339         pinctrl_uart4: uart4grp {
 340                 fsl,pins = <
 341                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 342                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 343                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 344                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 345                 >;
 346         };
 347
 348         pinctrl_uart5: uart5grp {
 349                 fsl,pins = <
 350                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x1b0b1
 351                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x1b0b1
 352                 >;
 353         };
 354
 355         pinctrl_usdhc4: usdhc4grp {
 356                 fsl,pins = <
 357                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 358                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 359                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 360                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 361                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 362                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 363                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 364                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 365                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 366                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 367                         MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059
 368                 >;
 369         };
 370 };