arch/arm/dts/fsl-ls1088a-qds.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1088a QDS common board device tree source
   4  *
   5  * Copyright 2017-2020 NXP
   6  */
   7
   8 #include "fsl-ls1088a.dtsi"
   9
  10 / {
  11         aliases {
  12                 spi0 = &qspi;
  13                 spi1 = &dspi;
  14         };
  15 };
  16
  17 &emdio1 {
  18         status = "okay";
  19 };
  20
  21 &emdio2 {
  22         status = "okay";
  23 };
  24
  25 &i2c0 {
  26         status = "okay";
  27         u-boot,dm-pre-reloc;
  28
  29         fpga@66 {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32                 compatible = "simple-mfd";
  33                 reg = <0x66>;
  34
  35                 mux-mdio@54 {
  36                         #address-cells = <1>;
  37                         #size-cells = <0>;
  38                         compatible = "mdio-mux-i2creg";
  39                         reg = <0x54>;
  40                         #mux-control-cells = <1>;
  41                         mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
  42                         mdio-parent-bus = <&emdio1>;
  43
  44                         mdio@00 {
  45                                 #address-cells = <1>;
  46                                 #size-cells = <0>;
  47                                 reg = <0x00>;
  48
  49                                 rgmii_phy1: ethernet-phy@1 {
  50                                         reg = <0x1>;
  51                                 };
  52                         };
  53                         mdio@20 {
  54                                 #address-cells = <1>;
  55                                 #size-cells = <0>;
  56                                 reg = <0x20>;
  57
  58                                 rgmii_phy2: ethernet-phy@2 {
  59                                         reg = <0x2>;
  60                                 };
  61                         };
  62
  63                         emdio1_slot1: mdio@40 { /* I/O Slot #1 */
  64                                 reg = <0x40>;
  65                                 device-name = "emdio1_slot1";
  66                                 #address-cells = <1>;
  67                                 #size-cells = <0>;
  68                         };
  69
  70                         emdio1_slot3: mdio@60 { /* I/O Slot #3 */
  71                                 reg = <0x60>;
  72                                 device-name = "emdio1_slot3";
  73                                 #address-cells = <1>;
  74                                 #size-cells = <0>;
  75                         };
  76                 };
  77         };
  78
  79         i2c-mux@77 {
  80                 compatible = "nxp,pca9547";
  81                 reg = <0x77>;
  82                 #address-cells = <1>;
  83                 #size-cells = <0>;
  84
  85                 i2c@3 {
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                         reg = <0x3>;
  89
  90                         rtc@51 {
  91                                 compatible = "pcf2127-rtc";
  92                                 reg = <0x51>;
  93                         };
  94                 };
  95         };
  96 };
  97
  98 &ifc {
  99         #address-cells = <2>;
 100         #size-cells = <1>;
 101         /* NOR, NAND Flashes and FPGA on board */
 102         ranges = <0 0 0x5 0x80000000 0x08000000
 103                         2 0 0x5 0x30000000 0x00010000
 104                         3 0 0x5 0x20000000 0x00010000>;
 105         status = "okay";
 106
 107         nor@0,0 {
 108                 #address-cells = <1>;
 109                 #size-cells = <1>;
 110                 compatible = "cfi-flash";
 111                 reg = <0x0 0x0 0x8000000>;
 112                 bank-width = <2>;
 113                 device-width = <1>;
 114         };
 115
 116         nand@2,0 {
 117                 compatible = "fsl,ifc-nand";
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 reg = <0x1 0x0 0x10000>;
 121         };
 122
 123         fpga: board-control@3,0 {
 124                 #address-cells = <1>;
 125                 #size-cells = <1>;
 126                 compatible = "simple-bus", "fsl,ls1088aqds-fpga",
 127                                 "fsl,fpga-qixis";
 128                 reg = <0x2 0x0 0x0000100>;
 129                 bank-width = <1>;
 130                 device-width = <1>;
 131                 ranges = <0 2 0 0x100>;
 132         };
 133 };
 134
 135 &dspi {
 136         bus-num = <0>;
 137         status = "okay";
 138
 139         dflash0: n25q128a {
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 compatible = "jedec,spi-nor";
 143                 reg = <0>;
 144                 spi-max-frequency = <1000000>; /* input clock */
 145         };
 146
 147         dflash1: sst25wf040b {
 148                 #address-cells = <1>;
 149                 #size-cells = <1>;
 150                 compatible = "jedec,spi-nor";
 151                 spi-max-frequency = <3500000>;
 152                 reg = <1>;
 153         };
 154
 155         dflash2: en25s64 {
 156                 #address-cells = <1>;
 157                 #size-cells = <1>;
 158                 compatible = "jedec,spi-nor";
 159                 spi-max-frequency = <3500000>;
 160                 reg = <2>;
 161         };
 162 };
 163
 164 &qspi {
 165         status = "okay";
 166
 167         s25fs512s0: flash@0 {
 168                 #address-cells = <1>;
 169                 #size-cells = <1>;
 170                 compatible = "jedec,spi-nor";
 171                 spi-max-frequency = <50000000>;
 172                 reg = <0>;
 173         };
 174
 175         s25fs512s1: flash@1 {
 176                 #address-cells = <1>;
 177                 #size-cells = <1>;
 178                 compatible = "jedec,spi-nor";
 179                 spi-max-frequency = <50000000>;
 180                 reg = <1>;
 181          };
 182 };
 183
 184 &sata {
 185         status = "okay";
 186 };