SPDX: Convert all of our multiple license tags to Linux Kernel style
[oweals/u-boot.git] / arch / arm / dts / fsl-ls1043a.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4  *
5  * Copyright (C) 2014-2015, Freescale Semiconductor
6  *
7  * Mingkai Hu <Mingkai.hu@freescale.com>
8  */
9
10 /include/ "skeleton64.dtsi"
11
12 / {
13         compatible = "fsl,ls1043a";
14         interrupt-parent = <&gic>;
15
16         sysclk: sysclk {
17                 compatible = "fixed-clock";
18                 #clock-cells = <0>;
19                 clock-frequency = <100000000>;
20                 clock-output-names = "sysclk";
21         };
22
23         gic: interrupt-controller@1400000 {
24                 compatible = "arm,gic-400";
25                 #interrupt-cells = <3>;
26                 interrupt-controller;
27                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
28                       <0x0 0x1402000 0 0x2000>, /* GICC */
29                       <0x0 0x1404000 0 0x2000>, /* GICH */
30                       <0x0 0x1406000 0 0x2000>; /* GICV */
31                 interrupts = <1 9 0xf08>;
32         };
33
34         soc {
35                 compatible = "simple-bus";
36                 #address-cells = <2>;
37                 #size-cells = <2>;
38                 ranges;
39
40                 clockgen: clocking@1ee1000 {
41                         compatible = "fsl,ls1043a-clockgen";
42                         reg = <0x0 0x1ee1000 0x0 0x1000>;
43                         #clock-cells = <2>;
44                         clocks = <&sysclk>;
45                 };
46
47                 dspi0: dspi@2100000 {
48                         compatible = "fsl,vf610-dspi";
49                         #address-cells = <1>;
50                         #size-cells = <0>;
51                         reg = <0x0 0x2100000 0x0 0x10000>;
52                         interrupts = <0 64 0x4>;
53                         clock-names = "dspi";
54                         clocks = <&clockgen 4 0>;
55                         num-cs = <6>;
56                         big-endian;
57                         status = "disabled";
58                 };
59
60                 dspi1: dspi@2110000 {
61                         compatible = "fsl,vf610-dspi";
62                         #address-cells = <1>;
63                         #size-cells = <0>;
64                         reg = <0x0 0x2110000 0x0 0x10000>;
65                         interrupts = <0 65 0x4>;
66                         clock-names = "dspi";
67                         clocks = <&clockgen 4 0>;
68                         num-cs = <6>;
69                         big-endian;
70                         status = "disabled";
71                 };
72
73                 ifc: ifc@1530000 {
74                         compatible = "fsl,ifc", "simple-bus";
75                         reg = <0x0 0x1530000 0x0 0x10000>;
76                         interrupts = <0 43 0x4>;
77                 };
78
79                 i2c0: i2c@2180000 {
80                         compatible = "fsl,vf610-i2c";
81                         #address-cells = <1>;
82                         #size-cells = <0>;
83                         reg = <0x0 0x2180000 0x0 0x10000>;
84                         interrupts = <0 56 0x4>;
85                         clock-names = "i2c";
86                         clocks = <&clockgen 4 0>;
87                         status = "disabled";
88                 };
89
90                 i2c1: i2c@2190000 {
91                         compatible = "fsl,vf610-i2c";
92                         #address-cells = <1>;
93                         #size-cells = <0>;
94                         reg = <0x0 0x2190000 0x0 0x10000>;
95                         interrupts = <0 57 0x4>;
96                         clock-names = "i2c";
97                         clocks = <&clockgen 4 0>;
98                         status = "disabled";
99                 };
100
101                 i2c2: i2c@21a0000 {
102                         compatible = "fsl,vf610-i2c";
103                         #address-cells = <1>;
104                         #size-cells = <0>;
105                         reg = <0x0 0x21a0000 0x0 0x10000>;
106                         interrupts = <0 58 0x4>;
107                         clock-names = "i2c";
108                         clocks = <&clockgen 4 0>;
109                         status = "disabled";
110                 };
111
112                 i2c3: i2c@21b0000 {
113                         compatible = "fsl,vf610-i2c";
114                         #address-cells = <1>;
115                         #size-cells = <0>;
116                         reg = <0x0 0x21b0000 0x0 0x10000>;
117                         interrupts = <0 59 0x4>;
118                         clock-names = "i2c";
119                         clocks = <&clockgen 4 0>;
120                         status = "disabled";
121                 };
122
123                 duart0: serial@21c0500 {
124                         compatible = "fsl,ns16550", "ns16550a";
125                         reg = <0x00 0x21c0500 0x0 0x100>;
126                         interrupts = <0 54 0x4>;
127                         clocks = <&clockgen 4 0>;
128                 };
129
130                 duart1: serial@21c0600 {
131                         compatible = "fsl,ns16550", "ns16550a";
132                         reg = <0x00 0x21c0600 0x0 0x100>;
133                         interrupts = <0 54 0x4>;
134                         clocks = <&clockgen 4 0>;
135                 };
136
137                 duart2: serial@21d0500 {
138                         compatible = "fsl,ns16550", "ns16550a";
139                         reg = <0x0 0x21d0500 0x0 0x100>;
140                         interrupts = <0 55 0x4>;
141                         clocks = <&clockgen 4 0>;
142                 };
143
144                 duart3: serial@21d0600 {
145                         compatible = "fsl,ns16550", "ns16550a";
146                         reg = <0x0 0x21d0600 0x0 0x100>;
147                         interrupts = <0 55 0x4>;
148                         clocks = <&clockgen 4 0>;
149                 };
150
151                 lpuart0: serial@2950000 {
152                         compatible = "fsl,ls1021a-lpuart";
153                         reg = <0x0 0x2950000 0x0 0x1000>;
154                         interrupts = <0 48 0x4>;
155                         clocks = <&sysclk>;
156                         clock-names = "ipg";
157                         status = "disabled";
158                 };
159
160                 lpuart1: serial@2960000 {
161                         compatible = "fsl,ls1021a-lpuart";
162                         reg = <0x0 0x2960000 0x0 0x1000>;
163                         interrupts = <0 49 0x4>;
164                         clocks = <&sysclk>;
165                         clock-names = "ipg";
166                         status = "disabled";
167                 };
168
169                 lpuart2: serial@2970000 {
170                         compatible = "fsl,ls1021a-lpuart";
171                         reg = <0x0 0x2970000 0x0 0x1000>;
172                         interrupts = <0 50 0x4>;
173                         clock-names = "ipg";
174                         clocks = <&sysclk>;
175                         status = "disabled";
176                 };
177
178                 lpuart3: serial@2980000 {
179                         compatible = "fsl,ls1021a-lpuart";
180                         reg = <0x0 0x2980000 0x0 0x1000>;
181                         interrupts = <0 51 0x4>;
182                         clocks = <&sysclk>;
183                         clock-names = "ipg";
184                         status = "disabled";
185                 };
186
187                 lpuart4: serial@2990000 {
188                         compatible = "fsl,ls1021a-lpuart";
189                         reg = <0x0 0x2990000 0x0 0x1000>;
190                         interrupts = <0 52 0x4>;
191                         clocks = <&sysclk>;
192                         clock-names = "ipg";
193                         status = "disabled";
194                 };
195
196                 lpuart5: serial@29a0000 {
197                         compatible = "fsl,ls1021a-lpuart";
198                         reg = <0x0 0x29a0000 0x0 0x1000>;
199                         interrupts = <0 53 0x4>;
200                         clocks = <&sysclk>;
201                         clock-names = "ipg";
202                         status = "disabled";
203                 };
204                 qspi: quadspi@1550000 {
205                         compatible = "fsl,vf610-qspi";
206                         #address-cells = <1>;
207                         #size-cells = <0>;
208                         reg = <0x0 0x1550000 0x0 0x10000>,
209                                 <0x0 0x40000000 0x0 0x4000000>;
210                         reg-names = "QuadSPI", "QuadSPI-memory";
211                         num-cs = <2>;
212                         big-endian;
213                         status = "disabled";
214                 };
215
216                 usb0: usb3@2f00000 {
217                         compatible = "fsl,layerscape-dwc3";
218                         reg = <0x0 0x2f00000 0x0 0x10000>;
219                         interrupts = <0 60 0x4>;
220                         dr_mode = "host";
221                 };
222
223                 usb1: usb3@3000000 {
224                         compatible = "fsl,layerscape-dwc3";
225                         reg = <0x0 0x3000000 0x0 0x10000>;
226                         interrupts = <0 61 0x4>;
227                         dr_mode = "host";
228                 };
229
230                 usb2: usb3@3100000 {
231                         compatible = "fsl,layerscape-dwc3";
232                         reg = <0x0 0x3100000 0x0 0x10000>;
233                         interrupts = <0 63 0x4>;
234                         dr_mode = "host";
235                 };
236
237                 pcie@3400000 {
238                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
239                         reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
240                                0x00 0x03410000 0x0 0x10000   /* lut registers */
241                                0x40 0x00000000 0x0 0x20000>; /* configuration space */
242                         reg-names = "dbi", "lut", "config";
243                         big-endian;
244                         #address-cells = <3>;
245                         #size-cells = <2>;
246                         device_type = "pci";
247                         bus-range = <0x0 0xff>;
248                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
249                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
250                 };
251
252                 pcie@3500000 {
253                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
254                         reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
255                                0x00 0x03510000 0x0 0x10000   /* lut registers */
256                                0x48 0x00000000 0x0 0x20000>; /* configuration space */
257                         reg-names = "dbi", "lut", "config";
258                         big-endian;
259                         #address-cells = <3>;
260                         #size-cells = <2>;
261                         device_type = "pci";
262                         num-lanes = <2>;
263                         bus-range = <0x0 0xff>;
264                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
265                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
266                 };
267
268                 pcie@3600000 {
269                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
270                         reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
271                                0x00 0x03610000 0x0 0x10000   /* lut registers */
272                                0x50 0x00000000 0x0 0x20000>; /* configuration space */
273                         reg-names = "dbi", "lut", "config";
274                         big-endian;
275                         #address-cells = <3>;
276                         #size-cells = <2>;
277                         device_type = "pci";
278                         bus-range = <0x0 0xff>;
279                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
280                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
281                 };
282         };
283 };