arch/arm/dts/fsl-ls1043a-qds.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   4  *
   5  * Copyright (C) 2015, Freescale Semiconductor
   6  *
   7  * Mingkai Hu <Mingkai.hu@freescale.com>
   8  */
   9
  10 /include/ "fsl-ls1043a.dtsi"
  11
  12 / {
  13         model = "LS1043A QDS Board";
  14         aliases {
  15                 spi0 = &qspi;
  16                 spi1 = &dspi0;
  17         };
  18 };
  19
  20 &dspi0 {
  21         bus-num = <0>;
  22         status = "okay";
  23
  24         dflash0: n25q128a {
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 compatible = "jedec,spi-nor";
  28                 spi-max-frequency = <1000000>; /* input clock */
  29                 spi-cpol;
  30                 spi-cpha;
  31                 reg = <0>;
  32         };
  33
  34         dflash1: sst25wf040b {
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 compatible = "jedec,spi-nor";
  38                 spi-max-frequency = <3500000>;
  39                 spi-cpol;
  40                 spi-cpha;
  41                 reg = <1>;
  42         };
  43
  44         dflash2: en25s64 {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 compatible = "jedec,spi-nor";
  48                 spi-max-frequency = <3500000>;
  49                 spi-cpol;
  50                 spi-cpha;
  51                 reg = <2>;
  52         };
  53 };
  54
  55 &qspi {
  56         status = "okay";
  57
  58         s25fl128s0: flash@0 {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 compatible = "jedec,spi-nor";
  62                 spi-max-frequency = <50000000>;
  63                 reg = <0>;
  64         };
  65 };
  66
  67 &i2c0 {
  68         status = "okay";
  69         pca9547@77 {
  70                 compatible = "philips,pca9547";
  71                 reg = <0x77>;
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74
  75                 i2c@0 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         reg = <0x0>;
  79
  80                         rtc@68 {
  81                                 compatible = "dallas,ds3232";
  82                                 reg = <0x68>;
  83                                 /* IRQ10_B */
  84                                 interrupts = <0 150 0x4>;
  85                         };
  86                 };
  87
  88                 i2c@2 {
  89                         #address-cells = <1>;
  90                         #size-cells = <0>;
  91                         reg = <0x2>;
  92
  93                         ina220@40 {
  94                                 compatible = "ti,ina220";
  95                                 reg = <0x40>;
  96                                 shunt-resistor = <1000>;
  97                         };
  98
  99                         ina220@41 {
 100                                 compatible = "ti,ina220";
 101                                 reg = <0x41>;
 102                                 shunt-resistor = <1000>;
 103                         };
 104                 };
 105
 106                 i2c@3 {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                         reg = <0x3>;
 110
 111                         eeprom@56 {
 112                                 compatible = "at24,24c512";
 113                                 reg = <0x56>;
 114                         };
 115
 116                         eeprom@57 {
 117                                 compatible = "at24,24c512";
 118                                 reg = <0x57>;
 119                         };
 120
 121                         adt7461a@4c {
 122                                 compatible = "adt7461a";
 123                                 reg = <0x4c>;
 124                         };
 125                 };
 126         };
 127 };
 128
 129 &ifc {
 130         #address-cells = <2>;
 131         #size-cells = <1>;
 132         /* NOR, NAND Flashes and FPGA on board */
 133         ranges = <0x0 0x0 0x0 0x60000000 0x08000000
 134                   0x1 0x0 0x0 0x7e800000 0x00010000
 135                   0x2 0x0 0x0 0x7fb00000 0x00000100>;
 136         status = "okay";
 137
 138         nor@0,0 {
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 compatible = "cfi-flash";
 142                 reg = <0x0 0x0 0x8000000>;
 143                 bank-width = <2>;
 144                 device-width = <1>;
 145         };
 146
 147         nand@1,0 {
 148                 compatible = "fsl,ifc-nand";
 149                 #address-cells = <1>;
 150                 #size-cells = <1>;
 151                 reg = <0x1 0x0 0x10000>;
 152         };
 153
 154         fpga: board-control@2,0 {
 155                 #address-cells = <1>;
 156                 #size-cells = <1>;
 157                 compatible = "simple-bus";
 158                 reg = <0x2 0x0 0x0000100>;
 159                 bank-width = <1>;
 160                 device-width = <1>;
 161                 ranges = <0 2 0 0x100>;
 162         };
 163 };
 164
 165 &duart0 {
 166         status = "okay";
 167 };
 168
 169 &duart1 {
 170         status = "okay";
 171 };
 172
 173 &lpuart0 {
 174         status = "okay";
 175 };
 176
 177 &sata {
 178         status = "okay";
 179 };