arch/arm/dts/fsl-ls1028a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1028a SOC common device tree source
   4  *
   5  * Copyright 2019 NXP
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "fsl,ls1028a";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         sysclk: sysclk {
  18                 compatible = "fixed-clock";
  19                 #clock-cells = <0>;
  20                 clock-frequency = <100000000>;
  21                 clock-output-names = "sysclk";
  22         };
  23
  24         clockgen: clocking@1300000 {
  25                 compatible = "fsl,ls1028a-clockgen";
  26                 reg = <0x0 0x1300000 0x0 0xa0000>;
  27                 #clock-cells = <2>;
  28                 clocks = <&sysclk>;
  29         };
  30
  31         memory@01080000 {
  32                 device_type = "memory";
  33                 reg = <0x00000000 0x01080000 0 0x80000000>;
  34                       /* DRAM space - 1, size : 2 GB DRAM */
  35         };
  36
  37         gic: interrupt-controller@6000000 {
  38                 compatible = "arm,gic-v3";
  39                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  40                           <0x0 0x06040000 0 0x40000>;
  41                 #interrupt-cells = <3>;
  42                 interrupt-controller;
  43                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
  44                                          IRQ_TYPE_LEVEL_LOW)>;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv8-timer";
  49                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  50                                           IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  52                                           IRQ_TYPE_LEVEL_LOW)>,
  53                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  54                                           IRQ_TYPE_LEVEL_LOW)>,
  55                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  56                                           IRQ_TYPE_LEVEL_LOW)>;
  57         };
  58
  59         fspi: flexspi@20c0000 {
  60                 compatible = "nxp,lx2160a-fspi";
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 reg = <0x0 0x20c0000 0x0 0x10000>,
  64                       <0x0 0x20000000 0x0 0x10000000>;
  65                 reg-names = "fspi_base", "fspi_mmap";
  66                 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  67                 clock-names = "fspi_en", "fspi";
  68                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  69                 status = "disabled";
  70         };
  71
  72         serial0: serial@21c0500 {
  73                 device_type = "serial";
  74                 compatible = "fsl,ns16550", "ns16550a";
  75                 reg = <0x0 0x21c0500 0x0 0x100>;
  76                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  77                 status = "disabled";
  78         };
  79
  80         serial1: serial@21c0600 {
  81                 device_type = "serial";
  82                 compatible = "fsl,ns16550", "ns16550a";
  83                 reg = <0x0 0x21c0600 0x0 0x100>;
  84                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  85                 status = "disabled";
  86         };
  87
  88         pcie@3400000 {
  89                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  90                reg = <0x00 0x03400000 0x0 0x80000
  91                        0x00 0x03480000 0x0 0x40000   /* lut registers */
  92                        0x00 0x034c0000 0x0 0x40000  /* pf controls registers */
  93                        0x80 0x00000000 0x0 0x20000>; /* configuration space */
  94                reg-names = "dbi", "lut", "ctrl", "config";
  95                #address-cells = <3>;
  96                #size-cells = <2>;
  97                device_type = "pci";
  98                num-lanes = <4>;
  99                bus-range = <0x0 0xff>;
 100                ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000   /* downstream I/O */
 101                        0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 102         };
 103
 104         pcie@3500000 {
 105                compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 106                reg = <0x00 0x03500000 0x0 0x80000
 107                        0x00 0x03580000 0x0 0x40000   /* lut registers */
 108                        0x00 0x035c0000 0x0 0x40000  /* pf controls registers */
 109                        0x88 0x00000000 0x0 0x20000>; /* configuration space */
 110                reg-names = "dbi", "lut", "ctrl", "config";
 111                #address-cells = <3>;
 112                #size-cells = <2>;
 113                device_type = "pci";
 114                num-lanes = <4>;
 115                bus-range = <0x0 0xff>;
 116                ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000   /* downstream I/O */
 117                        0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 118         };
 119
 120         pcie@1f0000000 {
 121                 compatible = "pci-host-ecam-generic";
 122                 /* ECAM bus 0, HW has more space reserved but not populated */
 123                 bus-range = <0x0 0x0>;
 124                 reg = <0x01 0xf0000000 0x0 0x100000>;
 125                 #address-cells = <3>;
 126                 #size-cells = <2>;
 127                 device_type = "pci";
 128                 ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
 129                 enetc0: pci@0,0 {
 130                         reg = <0x000000 0 0 0 0>;
 131                         status = "disabled";
 132                 };
 133                 enetc1: pci@0,1 {
 134                         reg = <0x000100 0 0 0 0>;
 135                         status = "disabled";
 136                 };
 137                 enetc2: pci@0,2 {
 138                         reg = <0x000200 0 0 0 0>;
 139                         status = "okay";
 140                         phy-mode = "internal";
 141                 };
 142                 mdio0: pci@0,3 {
 143                         #address-cells=<0>;
 144                         #size-cells=<1>;
 145                         reg = <0x000300 0 0 0 0>;
 146                         status = "disabled";
 147                 };
 148                 enetc6: pci@0,6 {
 149                         reg = <0x000600 0 0 0 0>;
 150                         status = "okay";
 151                         phy-mode = "internal";
 152                 };
 153         };
 154
 155         i2c0: i2c@2000000 {
 156                 compatible = "fsl,vf610-i2c";
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 reg = <0x0 0x2000000 0x0 0x10000>;
 160                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 161                 clock-names = "i2c";
 162                 clocks = <&clockgen 4 0>;
 163                 status = "disabled";
 164         };
 165
 166         i2c1: i2c@2010000 {
 167                 compatible = "fsl,vf610-i2c";
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 reg = <0x0 0x2010000 0x0 0x10000>;
 171                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 172                 clock-names = "i2c";
 173                 clocks = <&clockgen 4 0>;
 174                 status = "disabled";
 175         };
 176
 177         i2c2: i2c@2020000 {
 178                 compatible = "fsl,vf610-i2c";
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181                 reg = <0x0 0x2020000 0x0 0x10000>;
 182                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 183                 clock-names = "i2c";
 184                 clocks = <&clockgen 4 0>;
 185                 status = "disabled";
 186         };
 187
 188         i2c3: i2c@2030000 {
 189                 compatible = "fsl,vf610-i2c";
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 reg = <0x0 0x2030000 0x0 0x10000>;
 193                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 194                 clock-names = "i2c";
 195                 clocks = <&clockgen 4 0>;
 196                 status = "disabled";
 197         };
 198
 199         i2c4: i2c@2040000 {
 200                 compatible = "fsl,vf610-i2c";
 201                 #address-cells = <1>;
 202                 #size-cells = <0>;
 203                 reg = <0x0 0x2040000 0x0 0x10000>;
 204                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 205                 clock-names = "i2c";
 206                 clocks = <&clockgen 4 0>;
 207                 status = "disabled";
 208         };
 209
 210         i2c5: i2c@2050000 {
 211                 compatible = "fsl,vf610-i2c";
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 reg = <0x0 0x2050000 0x0 0x10000>;
 215                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 216                 clock-names = "i2c";
 217                 clocks = <&clockgen 4 0>;
 218                 status = "disabled";
 219         };
 220
 221         i2c6: i2c@2060000 {
 222                 compatible = "fsl,vf610-i2c";
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 reg = <0x0 0x2060000 0x0 0x10000>;
 226                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 227                 clock-names = "i2c";
 228                 clocks = <&clockgen 4 0>;
 229                 status = "disabled";
 230         };
 231
 232         i2c7: i2c@2070000 {
 233                 compatible = "fsl,vf610-i2c";
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 reg = <0x0 0x2070000 0x0 0x10000>;
 237                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 238                 clock-names = "i2c";
 239                 clocks = <&clockgen 4 0>;
 240                 status = "disabled";
 241         };
 242
 243         lpuart0: serial@2260000 {
 244                 compatible = "fsl,ls1021a-lpuart";
 245                 reg = <0x0 0x2260000 0x0 0x1000>;
 246                 interrupts = <0 232 0x4>;
 247                 clocks = <&sysclk>;
 248                 clock-names = "ipg";
 249                 little-endian;
 250                 status = "disabled";
 251         };
 252
 253         lpuart1: serial@2270000 {
 254                 compatible = "fsl,ls1021a-lpuart";
 255                 reg = <0x0 0x2270000 0x0 0x1000>;
 256                 interrupts = <0 233 0x4>;
 257                 clocks = <&sysclk>;
 258                 clock-names = "ipg";
 259                 little-endian;
 260                 status = "disabled";
 261         };
 262
 263         lpuart2: serial@2280000 {
 264                 compatible = "fsl,ls1021a-lpuart";
 265                 reg = <0x0 0x2280000 0x0 0x1000>;
 266                 interrupts = <0 234 0x4>;
 267                 clocks = <&sysclk>;
 268                 clock-names = "ipg";
 269                 little-endian;
 270                 status = "disabled";
 271         };
 272
 273         lpuart3: serial@2290000 {
 274                 compatible = "fsl,ls1021a-lpuart";
 275                 reg = <0x0 0x2290000 0x0 0x1000>;
 276                 interrupts = <0 235 0x4>;
 277                 clocks = <&sysclk>;
 278                 clock-names = "ipg";
 279                 little-endian;
 280                 status = "disabled";
 281         };
 282
 283         lpuart4: serial@22a0000 {
 284                 compatible = "fsl,ls1021a-lpuart";
 285                 reg = <0x0 0x22a0000 0x0 0x1000>;
 286                 interrupts = <0 236 0x4>;
 287                 clocks = <&sysclk>;
 288                 clock-names = "ipg";
 289                 little-endian;
 290                 status = "disabled";
 291         };
 292
 293         lpuart5: serial@22b0000 {
 294                 compatible = "fsl,ls1021a-lpuart";
 295                 reg = <0x0 0x22b0000 0x0 0x1000>;
 296                 interrupts = <0 237 0x4>;
 297                 clocks = <&sysclk>;
 298                 clock-names = "ipg";
 299                 little-endian;
 300                 status = "disabled";
 301         };
 302
 303         usb1: usb3@3100000 {
 304                 compatible = "fsl,layerscape-dwc3";
 305                 reg = <0x0 0x3100000 0x0 0x10000>;
 306                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 307                 dr_mode = "host";
 308                 status = "disabled";
 309         };
 310
 311         usb2: usb3@3110000 {
 312                 compatible = "fsl,layerscape-dwc3";
 313                 reg = <0x0 0x3110000 0x0 0x10000>;
 314                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 315                 dr_mode = "host";
 316                 status = "disabled";
 317         };
 318
 319         dspi0: dspi@2100000 {
 320                 compatible = "fsl,vf610-dspi";
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 reg = <0x0 0x2100000 0x0 0x10000>;
 324                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 325                 clock-names = "dspi";
 326                 clocks = <&clockgen 4 0>;
 327                 num-cs = <5>;
 328                 litte-endian;
 329                 status = "disabled";
 330         };
 331
 332         dspi1: dspi@2110000 {
 333                 compatible = "fsl,vf610-dspi";
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 reg = <0x0 0x2110000 0x0 0x10000>;
 337                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 338                 clock-names = "dspi";
 339                 clocks = <&clockgen 4 0>;
 340                 num-cs = <5>;
 341                 little-endian;
 342                 status = "disabled";
 343         };
 344
 345         dspi2: dspi@2120000 {
 346                 compatible = "fsl,vf610-dspi";
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 reg = <0x0 0x2120000 0x0 0x10000>;
 350                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 351                 clock-names = "dspi";
 352                 clocks = <&clockgen 4 0>;
 353                 num-cs = <5>;
 354                 little-endian;
 355                 status = "disabled";
 356         };
 357
 358         esdhc0: esdhc@2140000 {
 359                 compatible = "fsl,esdhc";
 360                 reg = <0x0 0x2140000 0x0 0x10000>;
 361                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 362                 big-endian;
 363                 bus-width = <4>;
 364                 status = "disabled";
 365         };
 366
 367         esdhc1: esdhc@2150000 {
 368                 compatible = "fsl,esdhc";
 369                 reg = <0x0 0x2150000 0x0 0x10000>;
 370                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 371                 big-endian;
 372                 non-removable;
 373                 bus-width = <4>;
 374                 status = "disabled";
 375         };
 376
 377         sata: sata@3200000 {
 378                 compatible = "fsl,ls1028a-ahci";
 379                 reg = <0x0 0x3200000 0x0 0x10000        /* ccsr sata base */
 380                        0x7 0x100520  0x0 0x4>;          /* ecc sata addr*/
 381                 reg-names = "sata-base", "ecc-addr";
 382                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 383                 status = "disabled";
 384         };
 385
 386         cluster1_core0_watchdog: wdt@c000000 {
 387                 compatible = "arm,sp805-wdt";
 388                 reg = <0x0 0xc000000 0x0 0x1000>;
 389         };
 390 };