arch/arm/dts/fsl-imx8qxp-colibri.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2019 Toradex AG
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "fsl-imx8qxp.dtsi"
   9 #include "fsl-imx8qxp-colibri-u-boot.dtsi"
  10
  11 / {
  12         model = "Toradex Colibri iMX8QXP";
  13         compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
  14
  15         chosen {
  16                 bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
  17                 stdout-path = &lpuart3;
  18         };
  19
  20         reg_usbh_vbus: regulator-usbh-vbus {
  21                 compatible = "regulator-fixed";
  22                 pinctrl-names = "default";
  23                 pinctrl-0 = <&pinctrl_usbh1_reg>;
  24                 regulator-name = "usbh_vbus";
  25                 regulator-min-microvolt = <5000000>;
  26                 regulator-max-microvolt = <5000000>;
  27                 gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
  28         };
  29 };
  30
  31 &iomuxc {
  32         pinctrl-names = "default";
  33         pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
  34
  35         colibri-imx8qxp {
  36                 pinctrl_lpuart0: lpuart0grp {
  37                         fsl,pins = <
  38                                 SC_P_UART0_RX_ADMA_UART0_RX     0x06000020
  39                                 SC_P_UART0_TX_ADMA_UART0_TX     0x06000020
  40                         >;
  41                 };
  42
  43                 pinctrl_lpuart3: lpuart3grp {
  44                         fsl,pins = <
  45                                 SC_P_FLEXCAN2_RX_ADMA_UART3_RX  0x06000020
  46                                 SC_P_FLEXCAN2_TX_ADMA_UART3_TX  0x06000020
  47                         >;
  48                 };
  49
  50                 pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
  51                         fsl,pins = <
  52                                 SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
  53                                 SC_P_SAI1_RXD_LSIO_GPIO0_IO29           0x00000020 /* CTS */
  54                                 SC_P_SAI1_RXC_LSIO_GPIO0_IO30           0x00000020 /* RTS */
  55                                 SC_P_CSI_RESET_LSIO_GPIO3_IO03          0x00000020 /* DSR */
  56                                 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22        0x00000020 /* DCD */
  57                                 SC_P_CSI_EN_LSIO_GPIO3_IO02             0x00000020 /* RI */
  58                         >;
  59                 };
  60
  61                 pinctrl_fec1: fec1grp {
  62                         fsl,pins = <
  63                                 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      0x000014a0 /* Use pads in 3.3V mode */
  64                                 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      0x000014a0 /* Use pads in 3.3V mode */
  65                                 SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000020
  66                                 SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000020
  67                                 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
  68                                 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT     0x06000061
  69                                 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x00000061
  70                                 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x00000061
  71                                 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
  72                                 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x00000061
  73                                 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x00000061
  74                                 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER     0x00000061
  75                         >;
  76                 };
  77
  78                 pinctrl_gpio_bl_on: gpio-bl-on {
  79                         fsl,pins = <
  80                                 SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12       0x00000040
  81                         >;
  82                 };
  83
  84                 pinctrl_hog0: hog0grp {
  85                         fsl,pins = <
  86                                 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  0x000514a0 /* Use pads in 3.3V mode */
  87                         >;
  88                 };
  89
  90                 pinctrl_hog1: hog1grp {
  91                         fsl,pins = <
  92                                 SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10       0x00000020 /*  45 */
  93                                 SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02   0x06000020 /*  65 */
  94                                         SC_P_CSI_D07_CI_PI_D09          0x00000061
  95                                 SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11       0x00000020 /*  69 */
  96                                 SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13         0x00000020 /*  73 */
  97                                 SC_P_SAI0_TXC_LSIO_GPIO0_IO26           0x00000020 /*  79 */
  98                                         SC_P_CSI_D02_CI_PI_D04          0x00000061
  99                                 SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03    0x06000020 /*  85 */
 100                                         SC_P_CSI_D06_CI_PI_D08          0x00000061
 101                                 SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17        0x00000020 /*  95 */
 102                                 SC_P_SAI0_RXD_LSIO_GPIO0_IO27           0x00000020 /*  97 */
 103                                         SC_P_CSI_D03_CI_PI_D05          0x00000061
 104                                 SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18       0x00000020 /*  99 */
 105                                 SC_P_SAI0_TXFS_LSIO_GPIO0_IO28          0x00000020 /* 101 */
 106                                         SC_P_CSI_D00_CI_PI_D02          0x00000061
 107                                 SC_P_SAI0_TXD_LSIO_GPIO0_IO25           0x00000020 /* 103 */
 108                                         SC_P_CSI_D01_CI_PI_D03          0x00000061
 109                                 SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19       0x00000020 /* 105 */
 110                                 SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20       0x00000020 /* 107 */
 111                                 SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05        0x00000020 /* 127 */
 112                                 SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06        0x00000020 /* 131 */
 113                                 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04        0x00000020 /* 133 */
 114                                 SC_P_CSI_PCLK_LSIO_GPIO3_IO00           0x00000020 /*  96 */
 115                                 SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21       0x00000020 /*  98 */
 116                                 SC_P_SAI1_RXFS_LSIO_GPIO0_IO31          0x00000020 /* 100 */
 117                                 SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22         0x00000020 /* 102 */
 118                                 SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23       0x00000020 /* 104 */
 119                                 SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24       0x00000020 /* 106 */
 120                         >;
 121                 };
 122
 123                 pinctrl_hog2: hog2grp {
 124                         fsl,pins = <
 125                                 SC_P_CSI_MCLK_LSIO_GPIO3_IO01           0x00000020 /*  75 */
 126                                 SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14       0x00000020 /*  77 */
 127                                 SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15       0x00000020 /*  89 */
 128                                 SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16        0x00000020 /*  93 */
 129                         >;
 130                 };
 131
 132                 /* Off Module I2C */
 133                 pinctrl_i2c1: i2c1grp {
 134                         fsl,pins = <
 135                                 SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL   0x06000021
 136                                 SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA   0x06000021
 137                         >;
 138                 };
 139
 140                 /*INT*/
 141                 pinctrl_usb3503a: usb3503a-grp {
 142                         fsl,pins = <
 143                                 SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
 144                         >;
 145                 };
 146
 147                 pinctrl_usbc_det: usbc-det {
 148                         fsl,pins = <
 149                                 SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09      0x06000040
 150                         >;
 151                 };
 152
 153                 pinctrl_usbh1_reg: usbh1-reg {
 154                         fsl,pins = <
 155                                 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03        0x06000040
 156                         >;
 157                 };
 158
 159                 pinctrl_usdhc1: usdhc1grp {
 160                         fsl,pins = <
 161                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
 162                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
 163                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
 164                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
 165                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
 166                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
 167                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
 168                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
 169                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
 170                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
 171                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
 172                                 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
 173                         >;
 174                 };
 175
 176                 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 177                         fsl,pins = <
 178                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
 179                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
 180                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
 181                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
 182                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
 183                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
 184                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
 185                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
 186                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
 187                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
 188                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
 189                                 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
 190                         >;
 191                 };
 192
 193                 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 194                         fsl,pins = <
 195                                 SC_P_EMMC0_CLK_CONN_EMMC0_CLK           0x06000041
 196                                 SC_P_EMMC0_CMD_CONN_EMMC0_CMD           0x00000021
 197                                 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0       0x00000021
 198                                 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1       0x00000021
 199                                 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2       0x00000021
 200                                 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3       0x00000021
 201                                 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4       0x00000021
 202                                 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5       0x00000021
 203                                 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6       0x00000021
 204                                 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7       0x00000021
 205                                 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE     0x00000041
 206                                 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B   0x00000021
 207                         >;
 208                 };
 209
 210                 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 211                         fsl,pins = <
 212                                 SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09       0x06000021
 213                         >;
 214                 };
 215
 216                 pinctrl_usdhc2: usdhc2grp {
 217                         fsl,pins = <
 218                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
 219                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
 220                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
 221                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
 222                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
 223                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
 224                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
 225                         >;
 226                 };
 227
 228                 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 229                         fsl,pins = <
 230                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
 231                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
 232                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
 233                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
 234                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
 235                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
 236                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
 237                         >;
 238                 };
 239
 240                 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 241                         fsl,pins = <
 242                                 SC_P_USDHC1_CLK_CONN_USDHC1_CLK         0x06000041
 243                                 SC_P_USDHC1_CMD_CONN_USDHC1_CMD         0x00000021
 244                                 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0     0x00000021
 245                                 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1     0x00000021
 246                                 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2     0x00000021
 247                                 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3     0x00000021
 248                                 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
 249                         >;
 250                 };
 251         };
 252 };
 253
 254 &lpuart0 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_lpuart0>;
 257         status = "okay";
 258 };
 259
 260 &lpuart3 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
 263         status = "okay";
 264 };
 265
 266 &gpio0 {
 267         status = "okay";
 268 };
 269
 270 &gpio1 {
 271         status = "okay";
 272 };
 273
 274 &gpio3 {
 275         status = "okay";
 276 };
 277
 278 &gpio4 {
 279         status = "okay";
 280 };
 281
 282 &fec1 {
 283         phy-handle = <&ethphy0>;
 284         phy-mode = "rmii";
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&pinctrl_fec1>;
 287         status = "okay";
 288
 289         mdio {
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292
 293                 ethphy0: ethernet-phy@2 {
 294                         compatible = "ethernet-phy-ieee802.3-c22";
 295                         max-speed = <100>;
 296                         reg = <2>;
 297                 };
 298         };
 299 };
 300
 301 &i2c1 {
 302         #address-cells = <1>;
 303         #size-cells = <0>;
 304         clock-frequency = <100000>;
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_i2c1>;
 307         status = "okay";
 308 };
 309
 310 &usdhc1 {
 311         bus-width = <8>;
 312         non-removable;
 313         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 314         pinctrl-0 = <&pinctrl_usdhc1>;
 315         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 316         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 317         status = "okay";
 318 };
 319
 320 &usdhc2 {
 321         bus-width = <4>;
 322         cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
 323         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 324         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 325         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 326         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 327         status = "okay";
 328 };