arch/arm/dts/exynos5420-peach-pit.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * SAMSUNG/GOOGLE Peach-Pit board device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 /dts-v1/;
  10 #include "exynos54xx.dtsi"
  11 #include <dt-bindings/clock/maxim,max77802.h>
  12 #include <dt-bindings/regulator/maxim,max77802.h>
  13
  14 / {
  15         model = "Samsung/Google Peach Pit board based on Exynos5420";
  16
  17         compatible = "google,pit-rev#", "google,pit",
  18                 "google,peach", "samsung,exynos5420", "samsung,exynos5";
  19
  20         config {
  21                 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
  22                 hwid = "PIT TEST A-A 7848";
  23                 lazy-init = <1>;
  24         };
  25
  26         aliases {
  27                 serial0 = "/serial@12C30000";
  28                 console = "/serial@12C30000";
  29                 pmic = "/i2c@12CA0000";
  30                 i2c104 = &i2c_tunnel;
  31         };
  32
  33         backlight: backlight {
  34                 compatible = "pwm-backlight";
  35                 pwms = <&pwm 0 1000000 0>;
  36                 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
  37                 default-brightness-level = <7>;
  38                 power-supply = <&tps65090_fet1>;
  39         };
  40
  41         dmc {
  42                 mem-manuf = "samsung";
  43                 mem-type = "ddr3";
  44                 clock-frequency = <800000000>;
  45                 arm-frequency = <900000000>;
  46         };
  47
  48         tmu@10060000 {
  49                 samsung,min-temp        = <25>;
  50                 samsung,max-temp        = <125>;
  51                 samsung,start-warning   = <95>;
  52                 samsung,start-tripping  = <105>;
  53                 samsung,hw-tripping     = <110>;
  54                 samsung,efuse-min-value = <40>;
  55                 samsung,efuse-value     = <55>;
  56                 samsung,efuse-max-value = <100>;
  57                 samsung,slope           = <274761730>;
  58                 samsung,dc-value        = <25>;
  59         };
  60
  61         /* MAX77802 is on i2c bus 4 */
  62         i2c@12CA0000 {
  63                 clock-frequency = <400000>;
  64                 power-regulator@9 {
  65                         compatible = "maxim,max77802-pmic";
  66                         reg = <0x9>;
  67                 };
  68         };
  69
  70         sound {
  71                 compatible = "google,peach-audio-max98090";
  72
  73                 samsung,model = "PEACH-I2S-MAX98090";
  74                 samsung,audio-codec = <&max98090>;
  75
  76                 cpu {
  77                         sound-dai = <&i2s0 0>;
  78                 };
  79
  80                 codec {
  81                         sound-dai = <&max98090 0>;
  82                 };
  83         };
  84
  85         i2c@12CD0000 { /* i2c7 */
  86                 clock-frequency = <100000>;
  87                 max98090: soundcodec@10 {
  88                         reg = <0x10>;
  89                         compatible = "maxim,max98090";
  90                         #sound-dai-cells = <1>;
  91                 };
  92
  93                 edp-lvds-bridge@48 {
  94                         compatible = "parade,ps8625";
  95                         reg = <0x48>;
  96                         sleep-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
  97                         reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>;
  98                         parade,regs = /bits/ 8 <
  99                                 0x02 0xa1 0x01  /* HPD low */
 100                                 /*
 101                                 * SW setting
 102                                 * [1:0] SW output 1.2V voltage is lower to 96%
 103                                 */
 104                                 0x04 0x14 0x01
 105                                 /*
 106                                 * RCO SS setting
 107                                 * [5:4] = b01 0.5%, b10 1%, b11 1.5%
 108                                 */
 109                                 0x04 0xe3 0x20
 110                                 0x04 0xe2 0x80 /* [7] RCO SS enable */
 111                                 /*
 112                                 *  RPHY Setting
 113                                 * [3:2] CDR tune wait cycle before
 114                                 * measure for fine tune b00: 1us,
 115                                 * 01: 0.5us, 10:2us, 11:4us.
 116                                 */
 117                                 0x04 0x8a 0x0c
 118                                 0x04 0x89 0x08 /* [3] RFD always on */
 119                                 /*
 120                                 * CTN lock in/out:
 121                                 * 20000ppm/80000ppm. Lock out 2
 122                                 * times.
 123                                 */
 124                                 0x04 0x71 0x2d
 125                                 /*
 126                                 * 2.7G CDR settings
 127                                 * NOF=40LSB for HBR CDR setting
 128                                 */
 129                                 0x04 0x7d 0x07
 130                                 0x04 0x7b 0x00  /* [1:0] Fmin=+4bands */
 131                                 0x04 0x7a 0xfd  /* [7:5] DCO_FTRNG=+-40% */
 132                                 /*
 133                                 * 1.62G CDR settings
 134                                 * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
 135                                 */
 136                                 0x04 0xc0 0x12
 137                                 0x04 0xc1 0x92  /* Gitune=-37% */
 138                                 0x04 0xc2 0x1c  /* Fbstep=100% */
 139                                 0x04 0x32 0x80  /* [7]LOS signal disable */
 140                                 /*
 141                                 * RPIO Setting
 142                                 * [7:4] LVDS driver bias current :
 143                                 * 75% (250mV swing)
 144                                 */
 145                                 0x04 0x00 0xb0
 146                                 /*
 147                                 * [7:6] Right-bar GPIO output strength is 8mA
 148                                 */
 149                                 0x04 0x15 0x40
 150                                 /* EQ Training State Machine Setting */
 151                                 0x04 0x54 0x10  /* RCO calibration start */
 152                                 /* [4:0] MAX_LANE_COUNT set to one lane */
 153                                 0x01 0x02 0x81
 154                                 /* [4:0] LANE_COUNT_SET set to one lane */
 155                                 0x01 0x21 0x81
 156                                 0x00 0x52 0x20
 157                                 0x00 0xf1 0x03  /* HPD CP toggle enable */
 158                                 0x00 0x62 0x41
 159                                 /* Counter number add 1ms counter delay */
 160                                 0x00 0xf6 0x01
 161                                 /*
 162                                 * [6]PWM function control by
 163                                 * DPCD0040f[7], default is PWM
 164                                 * block always works.
 165                                 */
 166                                 0x00 0x77 0x06
 167                                 /*
 168                                 * 04h Adjust VTotal tolerance to
 169                                 * fix the 30Hz no display issue
 170                                 */
 171                                 0x00 0x4c 0x04
 172                                 /* DPCD00400='h00, Parade OUI = 'h001cf8 */
 173                                 0x01 0xc0 0x00
 174                                 0x01 0xc1 0x1c  /* DPCD00401='h1c */
 175                                 0x01 0xc2 0xf8  /* DPCD00402='hf8 */
 176                                 /*
 177                                 * DPCD403~408 = ASCII code
 178                                 * D2SLV5='h4432534c5635
 179                                 */
 180                                 0x01 0xc3 0x44
 181                                 0x01 0xc4 0x32  /* DPCD404 */
 182                                 0x01 0xc5 0x53  /* DPCD405 */
 183                                 0x01 0xc6 0x4c  /* DPCD406 */
 184                                 0x01 0xc7 0x56  /* DPCD407 */
 185                                 0x01 0xc8 0x35  /* DPCD408 */
 186                                 /*
 187                                 * DPCD40A, Initial Code major  revision
 188                                 * '01'
 189                                 */
 190                                 0x01 0xca 0x01
 191                                 /* DPCD40B Initial Code minor revision '05' */
 192                                 0x01 0xcb 0x05
 193                                 /* DPCD720 Select internal PWM */
 194                                 0x01 0xa5 0xa0
 195                                 /*
 196                                 * FFh for 100% PWM of brightness, 0h for 0%
 197                                 * brightness
 198                                 */
 199                                 0x01 0xa7 0xff
 200                                 /*
 201                                 * Set LVDS output as 6bit-VESA mapping,
 202                                 * single LVDS channel
 203                                 */
 204                                 0x01 0xcc 0x13
 205                                 /* Enable SSC set by register */
 206                                 0x02 0xb1 0x20
 207                                 /*
 208                                 * Set SSC enabled and +/-1% central
 209                                 * spreading
 210                                 */
 211                                 0x04 0x10 0x16
 212                                 /* MPU Clock source: LC => RCO */
 213                                 0x04 0x59 0x60
 214                                 0x04 0x54 0x14  /* LC -> RCO */
 215                                 0x02 0xa1 0x91>;  /* HPD high */
 216
 217                         ports {
 218                                 port@0 {
 219                                         bridge_out: endpoint {
 220                                                 remote-endpoint = <&panel_in>;
 221                                         };
 222                                 };
 223
 224                                 port@1 {
 225                                         bridge_in: endpoint {
 226                                                 remote-endpoint = <&dp_out>;
 227                                         };
 228                                 };
 229                         };
 230                 };
 231         };
 232
 233         sound@3830000 {
 234                 samsung,codec-type = "max98090";
 235         };
 236
 237         i2c@12E10000 { /* i2c9 */
 238                 clock-frequency = <400000>;
 239                 tpm@20 {
 240                         compatible = "infineon,slb9645tt";
 241                         reg = <0x20>;
 242                 };
 243         };
 244
 245         panel: panel {
 246                 compatible = "auo,b116xw03";
 247                 power-supply = <&tps65090_fet6>;
 248                 backlight = <&backlight>;
 249
 250                 port {
 251                         panel_in: endpoint {
 252                                 remote-endpoint = <&bridge_out>;
 253                         };
 254                 };
 255         };
 256
 257         spi@12d30000 { /* spi1 */
 258                 spi-max-frequency = <50000000>;
 259                 firmware_storage_spi: flash@0 {
 260                         compatible = "spi-flash";
 261                         reg = <0>;
 262
 263                         /*
 264                          * A region for the kernel to store a panic event
 265                          * which the firmware will add to the log.
 266                         */
 267                         elog-panic-event-offset = <0x01e00000 0x100000>;
 268
 269                         elog-shrink-size = <0x400>;
 270                         elog-full-threshold = <0xc00>;
 271                 };
 272         };
 273
 274         xhci@12000000 {
 275                 samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
 276         };
 277
 278         xhci@12400000 {
 279                 samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
 280         };
 281
 282         fimd@14400000 {
 283                 samsung,vl-freq = <60>;
 284                 samsung,vl-col = <1366>;
 285                 samsung,vl-row = <768>;
 286                 samsung,vl-width = <1366>;
 287                 samsung,vl-height = <768>;
 288
 289                 samsung,vl-clkp;
 290                 samsung,vl-dp;
 291                 samsung,vl-bpix = <4>;
 292
 293                 samsung,vl-hspw = <32>;
 294                 samsung,vl-hbpd = <40>;
 295                 samsung,vl-hfpd = <40>;
 296                 samsung,vl-vspw = <6>;
 297                 samsung,vl-vbpd = <10>;
 298                 samsung,vl-vfpd = <12>;
 299                 samsung,vl-cmd-allow-len = <0xf>;
 300
 301                 samsung,winid = <3>;
 302                 samsung,interface-mode = <1>;
 303                 samsung,dp-enabled = <1>;
 304                 samsung,dual-lcd-enabled = <0>;
 305         };
 306 };
 307
 308 &dp {
 309         status = "okay";
 310         samsung,color-space = <0>;
 311         samsung,dynamic-range = <0>;
 312         samsung,ycbcr-coeff = <0>;
 313         samsung,color-depth = <1>;
 314         samsung,link-rate = <0x06>;
 315         samsung,lane-count = <2>;
 316         samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 317
 318         ports {
 319                 port@0 {
 320                         dp_out: endpoint {
 321                                 remote-endpoint = <&bridge_in>;
 322                         };
 323                 };
 324         };
 325 };
 326
 327 &spi_2 {
 328         spi-max-frequency = <3125000>;
 329         spi-deactivate-delay = <200>;
 330         status = "okay";
 331         num-cs = <1>;
 332         samsung,spi-src-clk = <0>;
 333         cs-gpios = <&gpb1 2 0>;
 334
 335         cros_ec: cros-ec@0 {
 336                 compatible = "google,cros-ec-spi";
 337                 interrupt-parent = <&gpx1>;
 338                 interrupts = <5 0>;
 339                 reg = <0>;
 340                 spi-half-duplex;
 341                 spi-max-timeout-ms = <1100>;
 342                 ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
 343                 #address-cells = <1>;
 344                 #size-cells = <1>;
 345
 346                 /*
 347                  * This describes the flash memory within the EC. Note
 348                  * that the STM32L flash erases to 0, not 0xff.
 349                  */
 350                 flash@8000000 {
 351                         reg = <0x08000000 0x20000>;
 352                         erase-value = <0>;
 353                 };
 354
 355                 controller-data {
 356                         samsung,spi-feedback-delay = <1>;
 357                 };
 358
 359                 i2c_tunnel: i2c-tunnel {
 360                         compatible = "google,cros-ec-i2c-tunnel";
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         google,remote-bus = <0>;
 364
 365                         battery: sbs-battery@b {
 366                                 compatible = "sbs,sbs-battery";
 367                                 reg = <0xb>;
 368                                 sbs,poll-retry-count = <1>;
 369                                 sbs,i2c-retry-count = <2>;
 370                         };
 371
 372                         power-regulator@48 {
 373                                 compatible = "ti,tps65090";
 374                                 reg = <0x48>;
 375
 376                                 regulators {
 377                                         tps65090_dcdc1: dcdc1 {
 378                                                 ti,enable-ext-control;
 379                                         };
 380                                         tps65090_dcdc2: dcdc2 {
 381                                                 ti,enable-ext-control;
 382                                         };
 383                                         tps65090_dcdc3: dcdc3 {
 384                                                 ti,enable-ext-control;
 385                                         };
 386                                         tps65090_fet1: fet1 {
 387                                                 regulator-name = "vcd_led";
 388                                         };
 389                                         tps65090_fet2: fet2 {
 390                                                 regulator-name = "video_mid";
 391                                                 regulator-always-on;
 392                                         };
 393                                         tps65090_fet3: fet3 {
 394                                                 regulator-name = "wwan_r";
 395                                                 regulator-always-on;
 396                                         };
 397                                         tps65090_fet4: fet4 {
 398                                                 regulator-name = "sdcard";
 399                                                 regulator-always-on;
 400                                         };
 401                                         tps65090_fet5: fet5 {
 402                                                 regulator-name = "camout";
 403                                                 regulator-always-on;
 404                                         };
 405                                         tps65090_fet6: fet6 {
 406                                                 regulator-name = "lcd_vdd";
 407                                         };
 408                                         tps65090_fet7: fet7 {
 409                                                 regulator-name = "video_mid_1a";
 410                                                 regulator-always-on;
 411                                         };
 412                                         tps65090_ldo1: ldo1 {
 413                                         };
 414                                         tps65090_ldo2: ldo2 {
 415                                         };
 416                                 };
 417
 418                                 charger {
 419                                         compatible = "ti,tps65090-charger";
 420                                 };
 421                         };
 422                 };
 423         };
 424 };
 425
 426 #include "cros-ec-keyboard.dtsi"