arch/arm/dts/bcm6858.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
   4  */
   5
   6 #include "skeleton64.dtsi"
   7
   8 / {
   9         compatible = "brcm,bcm6858";
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12
  13         aliases {
  14                 spi0 = &hsspi;
  15         };
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20                 u-boot,dm-pre-reloc;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "arm,cortex-a53", "arm,armv8";
  24                         device_type = "cpu";
  25                         reg = <0x0 0x0>;
  26                         next-level-cache = <&l2>;
  27                         u-boot,dm-pre-reloc;
  28                 };
  29
  30                 cpu1: cpu@1 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         device_type = "cpu";
  33                         reg = <0x0 0x1>;
  34                         next-level-cache = <&l2>;
  35                         u-boot,dm-pre-reloc;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         reg = <0x0 0x2>;
  42                         next-level-cache = <&l2>;
  43                         u-boot,dm-pre-reloc;
  44                 };
  45
  46                 cpu3: cpu@3 {
  47                         compatible = "arm,cortex-a53", "arm,armv8";
  48                         device_type = "cpu";
  49                         reg = <0x0 0x3>;
  50                         next-level-cache = <&l2>;
  51                         u-boot,dm-pre-reloc;
  52                 };
  53
  54                 l2: l2-cache0 {
  55                         compatible = "cache";
  56                         u-boot,dm-pre-reloc;
  57                 };
  58         };
  59
  60         clocks {
  61                 compatible = "simple-bus";
  62                 #address-cells = <2>;
  63                 #size-cells = <2>;
  64                 ranges;
  65                 u-boot,dm-pre-reloc;
  66
  67                 periph_osc: periph-osc {
  68                         compatible = "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <200000000>;
  71                         u-boot,dm-pre-reloc;
  72                 };
  73
  74                 hsspi_pll: hsspi-pll {
  75                         compatible = "fixed-factor-clock";
  76                         #clock-cells = <0>;
  77                         clocks = <&periph_osc>;
  78                         clock-mult = <2>;
  79                         clock-div = <1>;
  80                 };
  81
  82                 refclk50mhz: refclk50mhz {
  83                         compatible = "fixed-clock";
  84                         #clock-cells = <0>;
  85                         clock-frequency = <50000000>;
  86                 };
  87         };
  88
  89         ubus {
  90                 compatible = "simple-bus";
  91                 #address-cells = <2>;
  92                 #size-cells = <2>;
  93                 u-boot,dm-pre-reloc;
  94
  95                 uart0: serial@ff800640 {
  96                         compatible = "brcm,bcm6345-uart";
  97                         reg = <0x0 0xff800640 0x0 0x18>;
  98                         clocks = <&periph_osc>;
  99
 100                         status = "disabled";
 101                 };
 102
 103                 leds: led-controller@ff800800 {
 104                         compatible = "brcm,bcm6858-leds";
 105                         reg = <0x0 0xff800800 0x0 0xe4>;
 106
 107                         status = "disabled";
 108                 };
 109
 110                 wdt1: watchdog@ff802780 {
 111                         compatible = "brcm,bcm6345-wdt";
 112                         reg = <0x0 0xff802780 0x0 0x14>;
 113                         clocks = <&refclk50mhz>;
 114                 };
 115
 116                 wdt2: watchdog@ff8027c0 {
 117                         compatible = "brcm,bcm6345-wdt";
 118                         reg = <0x0 0xff8027c0 0x0 0x14>;
 119                         clocks = <&refclk50mhz>;
 120                 };
 121
 122                 wdt-reboot {
 123                         compatible = "wdt-reboot";
 124                         wdt = <&wdt1>;
 125                 };
 126
 127                 gpio0: gpio-controller@0xff800500 {
 128                         compatible = "brcm,bcm6345-gpio";
 129                         reg = <0x0 0xff800500 0x0 0x4>,
 130                               <0x0 0xff800520 0x0 0x4>;
 131                         gpio-controller;
 132                         #gpio-cells = <2>;
 133
 134                         status = "disabled";
 135                 };
 136
 137                 gpio1: gpio-controller@0xff800504 {
 138                         compatible = "brcm,bcm6345-gpio";
 139                         reg = <0x0 0xff800504 0x0 0x4>,
 140                               <0x0 0xff800524 0x0 0x4>;
 141                         gpio-controller;
 142                         #gpio-cells = <2>;
 143
 144                         status = "disabled";
 145                 };
 146
 147                 gpio2: gpio-controller@0xff800508 {
 148                         compatible = "brcm,bcm6345-gpio";
 149                         reg = <0x0 0xff800508 0x0 0x4>,
 150                               <0x0 0xff800528 0x0 0x4>;
 151                         gpio-controller;
 152                         #gpio-cells = <2>;
 153
 154                         status = "disabled";
 155                 };
 156
 157                 gpio3: gpio-controller@0xff80050c {
 158                         compatible = "brcm,bcm6345-gpio";
 159                         reg = <0x0 0xff80050c 0x0 0x4>,
 160                               <0x0 0xff80052c 0x0 0x4>;
 161                         gpio-controller;
 162                         #gpio-cells = <2>;
 163
 164                         status = "disabled";
 165                 };
 166
 167                 gpio4: gpio-controller@0xff800510 {
 168                         compatible = "brcm,bcm6345-gpio";
 169                         reg = <0x0 0xff800510 0x0 0x4>,
 170                               <0x0 0xff800530 0x0 0x4>;
 171                         gpio-controller;
 172                         #gpio-cells = <2>;
 173
 174                         status = "disabled";
 175                 };
 176
 177                 gpio5: gpio-controller@0xff800514 {
 178                         compatible = "brcm,bcm6345-gpio";
 179                         reg = <0x0 0xff800514 0x0 0x4>,
 180                               <0x0 0xff800534 0x0 0x4>;
 181                         gpio-controller;
 182                         #gpio-cells = <2>;
 183
 184                         status = "disabled";
 185                 };
 186
 187                 gpio6: gpio-controller@0xff800518 {
 188                         compatible = "brcm,bcm6345-gpio";
 189                         reg = <0x0 0xff800518 0x0 0x4>,
 190                               <0x0 0xff800538 0x0 0x4>;
 191                         gpio-controller;
 192                         #gpio-cells = <2>;
 193
 194                         status = "disabled";
 195                 };
 196
 197                 gpio7: gpio-controller@0xff80051c {
 198                         compatible = "brcm,bcm6345-gpio";
 199                         reg = <0x0 0xff80051c 0x0 0x4>,
 200                               <0x0 0xff80053c 0x0 0x4>;
 201                         gpio-controller;
 202                         #gpio-cells = <2>;
 203
 204                         status = "disabled";
 205                 };
 206
 207                 hsspi: spi-controller@ff801000 {
 208                         compatible = "brcm,bcm6328-hsspi";
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         reg = <0x0 0xff801000 0x0 0x600>;
 212                         clocks = <&hsspi_pll>, <&hsspi_pll>;
 213                         clock-names = "hsspi", "pll";
 214                         spi-max-frequency = <100000000>;
 215                         num-cs = <8>;
 216
 217                         status = "disabled";
 218                 };
 219
 220                 nand: nand-controller@ff801800 {
 221                         compatible = "brcm,nand-bcm6858",
 222                                      "brcm,brcmnand-v5.0",
 223                                      "brcm,brcmnand";
 224                         reg-names = "nand", "nand-int-base", "nand-cache";
 225                         reg = <0x0 0xff801800 0x0 0x180>,
 226                               <0x0 0xff802000 0x0 0x10>,
 227                               <0x0 0xff801c00 0x0 0x200>;
 228                         parameter-page-big-endian = <0>;
 229
 230                         status = "disabled";
 231                 };
 232         };
 233 };