arch/arm/dts/armada-385-db-88f6820-amc.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree file for Marvell Armada 385 AMC board
   4  * (DB-88F6820-AMC)
   5  *
   6  * Copyright (C) 2017 Allied Telesis Labs
   7  */
   8
   9 /dts-v1/;
  10 #include "armada-385.dtsi"
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         model = "Marvell Armada 385 AMC";
  16         compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
  17
  18         chosen {
  19                 stdout-path = "serial0:115200n8";
  20         };
  21
  22         aliases {
  23                 ethernet0 = &eth0;
  24                 ethernet1 = &eth2;
  25                 i2c0 = &i2c0;
  26                 spi1 = &spi1;
  27         };
  28
  29         memory {
  30                 device_type = "memory";
  31                 reg = <0x00000000 0x80000000>; /* 2GB */
  32         };
  33
  34         soc {
  35                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  36                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  37         };
  38 };
  39
  40 &i2c0 {
  41         u-boot,i2c-slave-addr = <0x0>;
  42         pinctrl-names = "default";
  43         pinctrl-0 = <&i2c0_pins>;
  44         status = "okay";
  45 };
  46
  47 &uart0 {
  48         /*
  49          * Exported on the micro USB connector CON3
  50          * through an FTDI
  51          */
  52
  53         pinctrl-names = "default";
  54         pinctrl-0 = <&uart0_pins>;
  55         status = "okay";
  56         u-boot,dm-pre-reloc;
  57 };
  58
  59
  60 &eth0 {
  61         pinctrl-names = "default";
  62         /*
  63          * The Reference Clock 0 is used to provide a
  64          * clock to the PHY
  65          */
  66         pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
  67         status = "okay";
  68         phy = <&phy0>;
  69         phy-mode = "rgmii-id";
  70 };
  71
  72 &eth2 {
  73         status = "okay";
  74         phy = <&phy1>;
  75         phy-mode = "sgmii";
  76 };
  77
  78 &usb0 {
  79         status = "okay";
  80 };
  81
  82
  83
  84 &mdio {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&mdio_pins>;
  87
  88         phy0: ethernet-phy@1 {
  89                 reg = <1>;
  90         };
  91
  92         phy1: ethernet-phy@0 {
  93                 reg = <0>;
  94         };
  95 };
  96
  97 &nand_controller {
  98         status = "okay";
  99         marvell,nand-keep-config;
 100         marvell,nand-enable-arbiter;
 101         nand-on-flash-bbt;
 102 };
 103
 104 &pciec {
 105         status = "okay";
 106 };
 107
 108 &pcie1 {
 109         /* Port 0, Lane 0 */
 110         status = "okay";
 111 };
 112
 113 &spi1 {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&spi1_pins>;
 116         status = "okay";
 117         u-boot,dm-pre-reloc;
 118
 119         spi-flash@0 {
 120                 u-boot,dm-pre-reloc;
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 compatible = "jedec,spi-nor";
 124                 reg = <0>; /* Chip select 0 */
 125                 spi-max-frequency = <50000000>;
 126                 m25p,fast-read;
 127
 128                 partitions {
 129                         compatible = "fixed-partitions";
 130                         #address-cells = <1>;
 131                         #size-cells = <1>;
 132                         partition@0 {
 133                                 reg = <0x00000000 0x00100000>;
 134                                 label = "u-boot";
 135                         };
 136                         partition@100000 {
 137                                 reg = <0x00100000 0x00040000>;
 138                                 label = "u-boot-env";
 139                         };
 140                 };
 141         };
 142 };
 143
 144 &refclk {
 145         clock-frequency = <20000000>;
 146 };