arch/arm/dts/armada-370-xp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  * Ben Dooks <ben.dooks@codethink.co.uk>
  11  *
  12  * This file contains the definitions that are common to the Armada
  13  * 370 and Armada XP SoC.
  14  */
  15
  16 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  17
  18 / {
  19         model = "Marvell Armada 370 and XP SoC";
  20         compatible = "marvell,armada-370-xp";
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30                 cpu@0 {
  31                         compatible = "marvell,sheeva-v7";
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                 };
  35         };
  36
  37         pmu {
  38                 compatible = "arm,cortex-a9-pmu";
  39                 interrupts-extended = <&mpic 3>;
  40         };
  41
  42         soc {
  43                 #address-cells = <2>;
  44                 #size-cells = <1>;
  45                 controller = <&mbusc>;
  46                 interrupt-parent = <&mpic>;
  47                 pcie-mem-aperture = <0xf8000000 0x7e00000>;
  48                 pcie-io-aperture  = <0xffe00000 0x100000>;
  49
  50                 devbus_bootcs: devbus-bootcs {
  51                         compatible = "marvell,mvebu-devbus";
  52                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  53                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  54                         #address-cells = <1>;
  55                         #size-cells = <1>;
  56                         clocks = <&coreclk 0>;
  57                         status = "disabled";
  58                 };
  59
  60                 devbus_cs0: devbus-cs0 {
  61                         compatible = "marvell,mvebu-devbus";
  62                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  63                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  64                         #address-cells = <1>;
  65                         #size-cells = <1>;
  66                         clocks = <&coreclk 0>;
  67                         status = "disabled";
  68                 };
  69
  70                 devbus_cs1: devbus-cs1 {
  71                         compatible = "marvell,mvebu-devbus";
  72                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  73                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  74                         #address-cells = <1>;
  75                         #size-cells = <1>;
  76                         clocks = <&coreclk 0>;
  77                         status = "disabled";
  78                 };
  79
  80                 devbus_cs2: devbus-cs2 {
  81                         compatible = "marvell,mvebu-devbus";
  82                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
  83                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
  84                         #address-cells = <1>;
  85                         #size-cells = <1>;
  86                         clocks = <&coreclk 0>;
  87                         status = "disabled";
  88                 };
  89
  90                 devbus_cs3: devbus-cs3 {
  91                         compatible = "marvell,mvebu-devbus";
  92                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
  93                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96                         clocks = <&coreclk 0>;
  97                         status = "disabled";
  98                 };
  99
 100                 internal-regs {
 101                         compatible = "simple-bus";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 105                         u-boot,dm-pre-reloc;
 106
 107                         rtc: rtc@10300 {
 108                                 compatible = "marvell,orion-rtc";
 109                                 reg = <0x10300 0x20>;
 110                                 interrupts = <50>;
 111                         };
 112
 113                         i2c0: i2c@11000 {
 114                                 compatible = "marvell,mv64xxx-i2c";
 115                                 #address-cells = <1>;
 116                                 #size-cells = <0>;
 117                                 interrupts = <31>;
 118                                 timeout-ms = <1000>;
 119                                 clocks = <&coreclk 0>;
 120                                 status = "disabled";
 121                         };
 122
 123                         i2c1: i2c@11100 {
 124                                 compatible = "marvell,mv64xxx-i2c";
 125                                 #address-cells = <1>;
 126                                 #size-cells = <0>;
 127                                 interrupts = <32>;
 128                                 timeout-ms = <1000>;
 129                                 clocks = <&coreclk 0>;
 130                                 status = "disabled";
 131                         };
 132
 133                         uart0: serial@12000 {
 134                                 compatible = "snps,dw-apb-uart";
 135                                 reg = <0x12000 0x100>;
 136                                 reg-shift = <2>;
 137                                 interrupts = <41>;
 138                                 reg-io-width = <1>;
 139                                 clocks = <&coreclk 0>;
 140                                 status = "disabled";
 141                         };
 142
 143                         uart1: serial@12100 {
 144                                 compatible = "snps,dw-apb-uart";
 145                                 reg = <0x12100 0x100>;
 146                                 reg-shift = <2>;
 147                                 interrupts = <42>;
 148                                 reg-io-width = <1>;
 149                                 clocks = <&coreclk 0>;
 150                                 status = "disabled";
 151                         };
 152
 153                         pinctrl: pin-ctrl@18000 {
 154                                 reg = <0x18000 0x38>;
 155                         };
 156
 157                         coredivclk: corediv-clock@18740 {
 158                                 compatible = "marvell,armada-370-corediv-clock";
 159                                 reg = <0x18740 0xc>;
 160                                 #clock-cells = <1>;
 161                                 clocks = <&mainpll>;
 162                                 clock-output-names = "nand";
 163                         };
 164
 165                         mbusc: mbus-controller@20000 {
 166                                 compatible = "marvell,mbus-controller";
 167                                 reg = <0x20000 0x100>, <0x20180 0x20>,
 168                                       <0x20250 0x8>;
 169                         };
 170
 171                         mpic: interrupt-controller@20a00 {
 172                                 compatible = "marvell,mpic";
 173                                 #interrupt-cells = <1>;
 174                                 #size-cells = <1>;
 175                                 interrupt-controller;
 176                                 msi-controller;
 177                         };
 178
 179                         coherencyfab: coherency-fabric@20200 {
 180                                 compatible = "marvell,coherency-fabric";
 181                                 reg = <0x20200 0xb0>, <0x21010 0x1c>;
 182                         };
 183
 184                         timer: timer@20300 {
 185                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 186                                 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
 187                         };
 188
 189                         watchdog: watchdog@20300 {
 190                                 reg = <0x20300 0x34>, <0x20704 0x4>;
 191                         };
 192
 193                         cpurst: cpurst@20800 {
 194                                 compatible = "marvell,armada-370-cpu-reset";
 195                                 reg = <0x20800 0x8>;
 196                         };
 197
 198                         pmsu: pmsu@22000 {
 199                                 compatible = "marvell,armada-370-pmsu";
 200                                 reg = <0x22000 0x1000>;
 201                         };
 202
 203                         usb0: usb@50000 {
 204                                 compatible = "marvell,orion-ehci";
 205                                 reg = <0x50000 0x500>;
 206                                 interrupts = <45>;
 207                                 status = "disabled";
 208                         };
 209
 210                         usb1: usb@51000 {
 211                                 compatible = "marvell,orion-ehci";
 212                                 reg = <0x51000 0x500>;
 213                                 interrupts = <46>;
 214                                 status = "disabled";
 215                         };
 216
 217                         eth0: ethernet@70000 {
 218                                 reg = <0x70000 0x4000>;
 219                                 interrupts = <8>;
 220                                 clocks = <&gateclk 4>;
 221                                 status = "disabled";
 222                         };
 223
 224                         mdio: mdio@72004 {
 225                                 #address-cells = <1>;
 226                                 #size-cells = <0>;
 227                                 compatible = "marvell,orion-mdio";
 228                                 reg = <0x72004 0x4>;
 229                                 clocks = <&gateclk 4>;
 230                         };
 231
 232                         eth1: ethernet@74000 {
 233                                 reg = <0x74000 0x4000>;
 234                                 interrupts = <10>;
 235                                 clocks = <&gateclk 3>;
 236                                 status = "disabled";
 237                         };
 238
 239                         sata: sata@a0000 {
 240                                 compatible = "marvell,armada-370-sata";
 241                                 reg = <0xa0000 0x5000>;
 242                                 interrupts = <55>;
 243                                 clocks = <&gateclk 15>, <&gateclk 30>;
 244                                 clock-names = "0", "1";
 245                                 status = "disabled";
 246                         };
 247
 248                         nand@d0000 {
 249                                 compatible = "marvell,armada370-nand";
 250                                 reg = <0xd0000 0x54>;
 251                                 #address-cells = <1>;
 252                                 #size-cells = <1>;
 253                                 interrupts = <113>;
 254                                 clocks = <&coredivclk 0>;
 255                                 status = "disabled";
 256                         };
 257
 258                         sdio: mvsdio@d4000 {
 259                                 compatible = "marvell,orion-sdio";
 260                                 reg = <0xd4000 0x200>;
 261                                 interrupts = <54>;
 262                                 clocks = <&gateclk 17>;
 263                                 bus-width = <4>;
 264                                 cap-sdio-irq;
 265                                 cap-sd-highspeed;
 266                                 cap-mmc-highspeed;
 267                                 status = "disabled";
 268                         };
 269                 };
 270
 271                 spi0: spi@10600 {
 272                         reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
 273                               <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
 274                               <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
 275                               <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
 276                               <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
 277                               <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
 278                               <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
 279                               <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
 280                               <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         cell-index = <0>;
 284                         interrupts = <30>;
 285                         clocks = <&coreclk 0>;
 286                         status = "disabled";
 287                 };
 288
 289                 spi1: spi@10680 {
 290                         reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
 291                               <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
 292                               <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
 293                               <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
 294                               <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
 295                               <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
 296                               <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
 297                               <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
 298                               <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         cell-index = <1>;
 302                         interrupts = <92>;
 303                         clocks = <&coreclk 0>;
 304                         status = "disabled";
 305                 };
 306         };
 307
 308         clocks {
 309                 /* 2 GHz fixed main PLL */
 310                 mainpll: mainpll {
 311                         compatible = "fixed-clock";
 312                         #clock-cells = <0>;
 313                         clock-frequency = <2000000000>;
 314                 };
 315         };
 316  };