1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor
8 #include <clock_legacy.h>
11 #include <fsl_immap.h>
14 #include <linux/sizes.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/soc.h>
18 #include <asm/cache.h>
20 #include <asm/global_data.h>
21 #include <asm/arch-fsl-layerscape/config.h>
22 #include <asm/arch-fsl-layerscape/ns_access.h>
23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
24 #include <asm/gic-v3.h>
25 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
28 #ifdef CONFIG_SYS_FSL_DDR
29 #include <fsl_ddr_sdram.h>
32 #ifdef CONFIG_CHAIN_OF_TRUST
33 #include <fsl_validate.h>
35 #include <fsl_immap.h>
37 #include <env_internal.h>
39 #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
40 DECLARE_GLOBAL_DATA_PTR;
43 #ifdef CONFIG_GIC_V3_ITS
44 #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
45 #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
46 #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
47 PROPTABLE_MAX_SZ, SZ_1M)
48 static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
52 struct fdt_memory gic_rd_tables;
54 gic_rd_tables.start = base;
55 gic_rd_tables.end = base + size - 1;
56 err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
59 debug("%s: failed to add reserved memory: %d\n", __func__, err);
64 int ls_gic_rd_tables_init(void *blob)
69 gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
70 ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
74 ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
76 debug("%s: failed to init gic-lpi-tables\n", __func__);
82 bool soc_has_dp_ddr(void)
84 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
85 u32 svr = gur_in32(&gur->svr);
87 /* LS2085A, LS2088A, LS2048A has DP_DDR */
88 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
89 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
90 (SVR_SOC_VER(svr) == SVR_LS2048A))
96 bool soc_has_aiop(void)
98 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
99 u32 svr = gur_in32(&gur->svr);
101 /* LS2085A has AIOP */
102 if (SVR_SOC_VER(svr) == SVR_LS2085A)
108 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
110 scfg_clrsetbits32(scfg + offset / 4,
112 SCFG_USB_TXVREFTUNE << 6);
115 static void erratum_a009008(void)
117 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
118 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
120 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
121 defined(CONFIG_ARCH_LS1012A)
122 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
123 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
124 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
125 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
127 #elif defined(CONFIG_ARCH_LS2080A)
128 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
130 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
133 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
135 scfg_clrbits32(scfg + offset / 4,
136 SCFG_USB_SQRXTUNE_MASK << 23);
139 static void erratum_a009798(void)
141 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
142 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
144 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
145 defined(CONFIG_ARCH_LS1012A)
146 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
147 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
148 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
149 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
151 #elif defined(CONFIG_ARCH_LS2080A)
152 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
154 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
157 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
158 defined(CONFIG_ARCH_LS1012A)
159 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
161 scfg_clrsetbits32(scfg + offset / 4,
163 SCFG_USB_PCSTXSWINGFULL << 9);
167 static void erratum_a008997(void)
169 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
170 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
171 defined(CONFIG_ARCH_LS1012A)
172 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
174 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
175 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
176 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
177 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
179 #elif defined(CONFIG_ARCH_LS1028A)
180 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
182 DCSR_USB_PCSTXSWINGFULL << 11);
184 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
187 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
188 defined(CONFIG_ARCH_LS1012A)
190 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
191 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
192 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
193 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
194 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
196 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
197 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
199 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
200 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
201 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
202 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
203 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
207 static void erratum_a009007(void)
209 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
210 defined(CONFIG_ARCH_LS1012A)
211 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
213 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
214 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
215 usb_phy = (void __iomem *)SCFG_USB_PHY2;
216 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
218 usb_phy = (void __iomem *)SCFG_USB_PHY3;
219 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
221 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
222 defined(CONFIG_ARCH_LS1028A)
223 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
225 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
226 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
227 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
230 #if defined(CONFIG_FSL_LSCH3)
231 static void erratum_a050106(void)
233 #if defined(CONFIG_ARCH_LX2160A)
234 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
236 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
237 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
241 * This erratum requires setting a value to eddrtqcr1 to
242 * optimal the DDR performance.
244 static void erratum_a008336(void)
246 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
249 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
250 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
251 if (fsl_ddr_get_version(0) == 0x50200)
252 out_le32(eddrtqcr1, 0x63b30002);
254 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
255 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
256 if (fsl_ddr_get_version(0) == 0x50200)
257 out_le32(eddrtqcr1, 0x63b30002);
263 * This erratum requires a register write before being Memory
264 * controller 3 being enabled.
266 static void erratum_a008514(void)
268 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
271 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
272 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
273 out_le32(eddrtqcr1, 0x63b20002);
277 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
278 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
280 static unsigned long get_internval_val_mhz(void)
282 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
284 * interval is the number of platform cycles(MHz) between
285 * wake up events generated by EPU.
287 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
290 interval_mhz = simple_strtoul(interval, NULL, 10);
295 void erratum_a009635(void)
298 unsigned long interval_mhz = get_internval_val_mhz();
303 val = in_le32(DCSR_CGACRE5);
304 writel(val | 0x00000200, DCSR_CGACRE5);
306 val = in_le32(EPU_EPCMPR5);
307 writel(interval_mhz, EPU_EPCMPR5);
308 val = in_le32(EPU_EPCCR5);
309 writel(val | 0x82820000, EPU_EPCCR5);
310 val = in_le32(EPU_EPSMCR5);
311 writel(val | 0x002f0000, EPU_EPSMCR5);
312 val = in_le32(EPU_EPECR5);
313 writel(val | 0x20000000, EPU_EPECR5);
314 val = in_le32(EPU_EPGCR);
315 writel(val | 0x80000000, EPU_EPGCR);
317 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
319 static void erratum_rcw_src(void)
321 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
322 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
323 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
326 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
327 val &= ~DCFG_PORSR1_RCW_SRC;
328 val |= DCFG_PORSR1_RCW_SRC_NOR;
329 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
333 #define I2C_DEBUG_REG 0x6
334 #define I2C_GLITCH_EN 0x8
336 * This erratum requires setting glitch_en bit to enable
337 * digital glitch filter to improve clock stability.
339 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
340 static void erratum_a009203(void)
342 #ifdef CONFIG_SYS_I2C
344 #ifdef I2C1_BASE_ADDR
345 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
347 writeb(I2C_GLITCH_EN, ptr);
349 #ifdef I2C2_BASE_ADDR
350 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
352 writeb(I2C_GLITCH_EN, ptr);
354 #ifdef I2C3_BASE_ADDR
355 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
357 writeb(I2C_GLITCH_EN, ptr);
359 #ifdef I2C4_BASE_ADDR
360 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
362 writeb(I2C_GLITCH_EN, ptr);
368 void bypass_smmu(void)
371 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
372 out_le32(SMMU_SCR0, val);
373 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
374 out_le32(SMMU_NSCR0, val);
376 void fsl_lsch3_early_init_f(void)
379 #ifdef CONFIG_FSL_IFC
380 init_early_memctl_regs(); /* tighten IFC timing */
382 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
392 #ifdef CONFIG_CHAIN_OF_TRUST
393 /* In case of Secure Boot, the IBR configures the SMMU
394 * to allow only Secure transactions.
395 * SMMU must be reset in bypass mode.
396 * Set the ClientPD bit and Clear the USFCFG Bit
398 if (fsl_check_boot_mode_secure() == 1)
402 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
403 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
408 /* Get VDD in the unit mV from voltage ID */
409 int get_core_volt_from_fuse(void)
411 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
416 /* get the voltage ID from fuse status register */
417 fusesr = in_le32(&gur->dcfg_fusesr);
418 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
419 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
420 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
421 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
422 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
423 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
425 debug("%s: VID = 0x%x\n", __func__, vid);
427 case 0x00: /* VID isn't supported */
429 debug("%s: The VID feature is not supported\n", __func__);
431 case 0x08: /* 0.9V silicon */
434 case 0x10: /* 1.0V silicon */
437 default: /* Other core voltage */
439 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
442 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
447 #elif defined(CONFIG_FSL_LSCH2)
449 static void erratum_a009929(void)
451 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
452 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
453 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
454 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
456 rstrqmr1 |= 0x00000400;
457 gur_out32(&gur->rstrqmr1, rstrqmr1);
458 writel(0x01000000, dcsr_cop_ccp);
463 * This erratum requires setting a value to eddrtqcr1 to optimal
464 * the DDR performance. The eddrtqcr1 register is in SCFG space
465 * of LS1043A and the offset is 0x157_020c.
467 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
468 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
469 #error A009660 and A008514 can not be both enabled.
472 static void erratum_a009660(void)
474 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
475 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
476 out_be32(eddrtqcr1, 0x63b20042);
480 static void erratum_a008850_early(void)
482 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
484 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
485 CONFIG_SYS_CCI400_OFFSET);
486 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
488 /* Skip if running at lower exception level */
489 if (current_el() < 3)
492 /* disables propagation of barrier transactions to DDRC from CCI400 */
493 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
495 /* disable the re-ordering in DDRC */
496 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
500 void erratum_a008850_post(void)
502 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
504 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
505 CONFIG_SYS_CCI400_OFFSET);
506 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
509 /* Skip if running at lower exception level */
510 if (current_el() < 3)
513 /* enable propagation of barrier transactions to DDRC from CCI400 */
514 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
516 /* enable the re-ordering in DDRC */
517 tmp = ddr_in32(&ddr->eor);
518 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
519 ddr_out32(&ddr->eor, tmp);
523 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
524 void erratum_a010315(void)
528 for (i = PCIE1; i <= PCIE4; i++)
529 if (!is_serdes_configured(i)) {
530 debug("PCIe%d: disabled all R/W permission!\n", i);
531 set_pcie_ns_access(i, 0);
536 static void erratum_a010539(void)
538 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
539 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
542 porsr1 = in_be32(&gur->porsr1);
543 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
544 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
546 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
550 /* Get VDD in the unit mV from voltage ID */
551 int get_core_volt_from_fuse(void)
553 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
558 fusesr = in_be32(&gur->dcfg_fusesr);
559 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
560 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
561 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
562 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
563 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
564 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
566 debug("%s: VID = 0x%x\n", __func__, vid);
568 case 0x00: /* VID isn't supported */
570 debug("%s: The VID feature is not supported\n", __func__);
572 case 0x08: /* 0.9V silicon */
575 case 0x10: /* 1.0V silicon */
578 default: /* Other core voltage */
580 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
583 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
588 __weak int board_switch_core_volt(u32 vdd)
593 static int setup_core_volt(u32 vdd)
595 return board_setup_core_volt(vdd);
598 #ifdef CONFIG_SYS_FSL_DDR
599 static void ddr_enable_0v9_volt(bool en)
601 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
604 tmp = ddr_in32(&ddr->ddr_cdr1);
607 tmp |= DDR_CDR1_V0PT9_EN;
609 tmp &= ~DDR_CDR1_V0PT9_EN;
611 ddr_out32(&ddr->ddr_cdr1, tmp);
615 int setup_chip_volt(void)
619 vdd = get_core_volt_from_fuse();
620 /* Nothing to do for silicons doesn't support VID */
624 if (setup_core_volt(vdd))
625 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
626 #ifdef CONFIG_SYS_HAS_SERDES
627 if (setup_serdes_volt(vdd))
628 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
631 #ifdef CONFIG_SYS_FSL_DDR
633 ddr_enable_0v9_volt(true);
639 #ifdef CONFIG_FSL_PFE
640 void init_pfe_scfg_dcfg_regs(void)
642 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
645 out_be32(&scfg->pfeasbcr,
646 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
647 out_be32(&scfg->pfebsbcr,
648 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
650 /* CCI-400 QoS settings for PFE */
651 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
652 | SCFG_WR_QOS1_PFE2_QOS));
653 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
654 | SCFG_RD_QOS1_PFE2_QOS));
656 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
657 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
658 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
662 void fsl_lsch2_early_init_f(void)
664 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
665 CONFIG_SYS_CCI400_OFFSET);
666 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
667 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
671 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
672 enable_layerscape_ns_access();
675 #ifdef CONFIG_FSL_IFC
676 init_early_memctl_regs(); /* tighten IFC timing */
679 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
680 src = get_boot_src();
681 if (src != BOOT_SOURCE_QSPI_NOR)
682 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
684 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
685 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
688 /* Make SEC reads and writes snoopable */
689 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
690 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
691 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
692 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
693 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
694 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
695 SCFG_SNPCNFGCR_SATAWRSNP);
696 #elif defined(CONFIG_ARCH_LS1012A)
697 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
698 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
699 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
700 SCFG_SNPCNFGCR_SATAWRSNP);
702 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
703 SCFG_SNPCNFGCR_SECWRSNP |
704 SCFG_SNPCNFGCR_SATARDSNP |
705 SCFG_SNPCNFGCR_SATAWRSNP);
709 * Enable snoop requests and DVM message requests for
710 * Slave insterface S4 (A53 core cluster)
712 if (current_el() == 3) {
713 out_le32(&cci->slave[4].snoop_ctrl,
714 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
718 * Program Central Security Unit (CSU) to grant access
719 * permission for USB 2.0 controller
721 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
722 if (current_el() == 3)
723 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
726 erratum_a008850_early(); /* part 1 of 2 */
735 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
741 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
742 int fspi_ahb_init(void)
744 /* Enable 4bytes address support and fast read */
745 u32 *fspi_lut, lut_key, *fspi_key;
747 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
748 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
750 lut_key = in_be32(fspi_key);
752 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
753 /* That means the register is BE */
754 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
755 /* Unlock the lut table */
756 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
757 /* Create READ LUT */
758 out_be32(fspi_lut, 0x0820040c);
759 out_be32(fspi_lut + 1, 0x24003008);
760 out_be32(fspi_lut + 2, 0x00000000);
761 /* Lock the lut table */
762 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
763 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
765 /* That means the register is LE */
766 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
767 /* Unlock the lut table */
768 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
769 /* Create READ LUT */
770 out_le32(fspi_lut, 0x0820040c);
771 out_le32(fspi_lut + 1, 0x24003008);
772 out_le32(fspi_lut + 2, 0x00000000);
773 /* Lock the lut table */
774 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
775 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
782 #ifdef CONFIG_QSPI_AHB_INIT
783 /* Enable 4bytes address support and fast read */
784 int qspi_ahb_init(void)
786 u32 *qspi_lut, lut_key, *qspi_key;
788 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
789 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
791 lut_key = in_be32(qspi_key);
793 if (lut_key == 0x5af05af0) {
794 /* That means the register is BE */
795 out_be32(qspi_key, 0x5af05af0);
796 /* Unlock the lut table */
797 out_be32(qspi_key + 1, 0x00000002);
798 out_be32(qspi_lut, 0x0820040c);
799 out_be32(qspi_lut + 1, 0x1c080c08);
800 out_be32(qspi_lut + 2, 0x00002400);
801 /* Lock the lut table */
802 out_be32(qspi_key, 0x5af05af0);
803 out_be32(qspi_key + 1, 0x00000001);
805 /* That means the register is LE */
806 out_le32(qspi_key, 0x5af05af0);
807 /* Unlock the lut table */
808 out_le32(qspi_key + 1, 0x00000002);
809 out_le32(qspi_lut, 0x0820040c);
810 out_le32(qspi_lut + 1, 0x1c080c08);
811 out_le32(qspi_lut + 2, 0x00002400);
812 /* Lock the lut table */
813 out_le32(qspi_key, 0x5af05af0);
814 out_le32(qspi_key + 1, 0x00000001);
821 #ifdef CONFIG_TFABOOT
822 #define MAX_BOOTCMD_SIZE 512
824 int fsl_setenv_bootcmd(void)
827 enum boot_src src = get_boot_src();
828 char bootcmd_str[MAX_BOOTCMD_SIZE];
831 #ifdef IFC_NOR_BOOTCOMMAND
832 case BOOT_SOURCE_IFC_NOR:
833 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
836 #ifdef QSPI_NOR_BOOTCOMMAND
837 case BOOT_SOURCE_QSPI_NOR:
838 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
841 #ifdef XSPI_NOR_BOOTCOMMAND
842 case BOOT_SOURCE_XSPI_NOR:
843 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
846 #ifdef IFC_NAND_BOOTCOMMAND
847 case BOOT_SOURCE_IFC_NAND:
848 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
851 #ifdef QSPI_NAND_BOOTCOMMAND
852 case BOOT_SOURCE_QSPI_NAND:
853 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
856 #ifdef XSPI_NAND_BOOTCOMMAND
857 case BOOT_SOURCE_XSPI_NAND:
858 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
861 #ifdef SD_BOOTCOMMAND
862 case BOOT_SOURCE_SD_MMC:
863 sprintf(bootcmd_str, SD_BOOTCOMMAND);
866 #ifdef SD2_BOOTCOMMAND
867 case BOOT_SOURCE_SD_MMC2:
868 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
872 #ifdef QSPI_NOR_BOOTCOMMAND
873 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
878 ret = env_set("bootcmd", bootcmd_str);
880 printf("Failed to set bootcmd: ret = %d\n", ret);
886 int fsl_setenv_mcinitcmd(void)
889 enum boot_src src = get_boot_src();
892 #ifdef IFC_MC_INIT_CMD
893 case BOOT_SOURCE_IFC_NAND:
894 case BOOT_SOURCE_IFC_NOR:
895 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
898 #ifdef QSPI_MC_INIT_CMD
899 case BOOT_SOURCE_QSPI_NAND:
900 case BOOT_SOURCE_QSPI_NOR:
901 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
904 #ifdef XSPI_MC_INIT_CMD
905 case BOOT_SOURCE_XSPI_NAND:
906 case BOOT_SOURCE_XSPI_NOR:
907 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
910 #ifdef SD_MC_INIT_CMD
911 case BOOT_SOURCE_SD_MMC:
912 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
915 #ifdef SD2_MC_INIT_CMD
916 case BOOT_SOURCE_SD_MMC2:
917 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
921 #ifdef QSPI_MC_INIT_CMD
922 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
928 printf("Failed to set mcinitcmd: ret = %d\n", ret);
935 #ifdef CONFIG_BOARD_LATE_INIT
936 __weak int fsl_board_late_init(void)
941 int board_late_init(void)
943 #ifdef CONFIG_CHAIN_OF_TRUST
944 fsl_setenv_chain_of_trust();
946 #ifdef CONFIG_TFABOOT
948 * check if gd->env_addr is default_environment; then setenv bootcmd
951 #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
952 if (gd->env_addr == (ulong)&default_environment[0]) {
954 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
956 fsl_setenv_bootcmd();
957 fsl_setenv_mcinitcmd();
961 * If the boot mode is secure, default environment is not present then
962 * setenv command needs to be run by default
964 #ifdef CONFIG_CHAIN_OF_TRUST
965 if ((fsl_check_boot_mode_secure() == 1)) {
966 fsl_setenv_bootcmd();
967 fsl_setenv_mcinitcmd();
971 #ifdef CONFIG_QSPI_AHB_INIT
974 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
978 return fsl_board_late_init();