arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016-2018 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <log.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/soc.h>
  14 #include <fsl-mc/ldpaa_wriop.h>
  15
  16 #ifdef CONFIG_SYS_FSL_SRDS_1
  17 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  18 #endif
  19 #ifdef CONFIG_SYS_FSL_SRDS_2
  20 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  21 #endif
  22 #ifdef CONFIG_SYS_NXP_SRDS_3
  23 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  24 #endif
  25
  26 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  27 #ifdef CONFIG_ARCH_LX2160A
  28 int xfi_dpmac[XFI14 + 1];
  29 int sgmii_dpmac[SGMII18 + 1];
  30 int a25gaui_dpmac[_25GE10 + 1];
  31 int xlaui_dpmac[_40GE2 + 1];
  32 int caui2_dpmac[_50GE2 + 1];
  33 int caui4_dpmac[_100GE2 + 1];
  34 #else
  35 int xfi_dpmac[XFI8 + 1];
  36 int sgmii_dpmac[SGMII16 + 1];
  37 #endif
  38 #endif
  39
  40 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  41 {
  42         return;
  43 }
  44
  45 /*
  46  *The return value of this func is the serdes protocol used.
  47  *Typically this function is called number of times depending
  48  *upon the number of serdes blocks in the Silicon.
  49  *Zero is used to denote that no serdes was enabled,
  50  *this is the case when golden RCW was used where DPAA2 bring was
  51  *intentionally removed to achieve boot to prompt
  52 */
  53
  54 __weak int serdes_get_number(int serdes, int cfg)
  55 {
  56         return cfg;
  57 }
  58
  59 int is_serdes_configured(enum srds_prtcl device)
  60 {
  61         int ret = 0;
  62
  63 #ifdef CONFIG_SYS_FSL_SRDS_1
  64         if (!serdes1_prtcl_map[NONE])
  65                 fsl_serdes_init();
  66
  67         ret |= serdes1_prtcl_map[device];
  68 #endif
  69 #ifdef CONFIG_SYS_FSL_SRDS_2
  70         if (!serdes2_prtcl_map[NONE])
  71                 fsl_serdes_init();
  72
  73         ret |= serdes2_prtcl_map[device];
  74 #endif
  75 #ifdef CONFIG_SYS_NXP_SRDS_3
  76         if (!serdes3_prtcl_map[NONE])
  77                 fsl_serdes_init();
  78
  79         ret |= serdes3_prtcl_map[device];
  80 #endif
  81
  82         return !!ret;
  83 }
  84
  85 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  86 {
  87         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  88         u32 cfg = 0;
  89         int i;
  90
  91         switch (sd) {
  92 #ifdef CONFIG_SYS_FSL_SRDS_1
  93         case FSL_SRDS_1:
  94                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  95                 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  96                 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  97                 break;
  98 #endif
  99 #ifdef CONFIG_SYS_FSL_SRDS_2
 100         case FSL_SRDS_2:
 101                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 102                 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
 103                 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
 104                 break;
 105 #endif
 106 #ifdef CONFIG_SYS_NXP_SRDS_3
 107         case NXP_SRDS_3:
 108                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 109                 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
 110                 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
 111                 break;
 112 #endif
 113         default:
 114                 printf("invalid SerDes%d\n", sd);
 115                 break;
 116         }
 117
 118         cfg = serdes_get_number(sd, cfg);
 119
 120         /* Is serdes enabled at all? */
 121         if (cfg == 0)
 122                 return -ENODEV;
 123
 124         for (i = 0; i < SRDS_MAX_LANES; i++) {
 125                 if (serdes_get_prtcl(sd, cfg, i) == device)
 126                         return i;
 127         }
 128
 129         return -ENODEV;
 130 }
 131
 132 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 133                  u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 134 {
 135         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 136         u32 cfg;
 137         int lane;
 138
 139         if (serdes_prtcl_map[NONE])
 140                 return;
 141
 142         memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 143
 144         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 145         cfg >>= sd_prctl_shift;
 146
 147         cfg = serdes_get_number(sd, cfg);
 148         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 149
 150         if (!is_serdes_prtcl_valid(sd, cfg))
 151                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 152
 153         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 154                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 155                 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
 156                         debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
 157                 else {
 158                         serdes_prtcl_map[lane_prtcl] = 1;
 159 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 160 #ifdef CONFIG_ARCH_LX2160A
 161                         if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
 162                                 wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
 163                                                  (int)lane_prtcl);
 164
 165                         if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
 166                                 wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
 167                                                  (int)lane_prtcl);
 168
 169                         if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
 170                                 wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
 171                                                  (int)lane_prtcl);
 172
 173                         if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
 174                                 wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
 175                                                  (int)lane_prtcl);
 176
 177                         if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
 178                                 wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
 179                                                  (int)lane_prtcl);
 180
 181                         if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
 182                                 wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
 183                                                  (int)lane_prtcl);
 184
 185 #else
 186                         switch (lane_prtcl) {
 187                         case QSGMII_A:
 188                         case QSGMII_B:
 189                         case QSGMII_C:
 190                         case QSGMII_D:
 191                                 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 192                                 break;
 193                         default:
 194                                 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
 195                                         wriop_init_dpmac(sd,
 196                                                          xfi_dpmac[lane_prtcl],
 197                                                          (int)lane_prtcl);
 198
 199                                  if (lane_prtcl >= SGMII1 &&
 200                                      lane_prtcl <= SGMII16)
 201                                         wriop_init_dpmac(sd, sgmii_dpmac[
 202                                                          lane_prtcl],
 203                                                          (int)lane_prtcl);
 204                                 break;
 205                         }
 206 #endif
 207 #endif
 208                 }
 209         }
 210
 211         /* Set the first element to indicate serdes has been initialized */
 212         serdes_prtcl_map[NONE] = 1;
 213 }
 214
 215 __weak int get_serdes_volt(void)
 216 {
 217         return -1;
 218 }
 219
 220 __weak int set_serdes_volt(int svdd)
 221 {
 222         return -1;
 223 }
 224
 225 #define LNAGCR0_RT_RSTB         0x00600000
 226
 227 #define RSTCTL_RESET_MASK       0x000000E0
 228
 229 #define RSTCTL_RSTREQ           0x80000000
 230 #define RSTCTL_RST_DONE         0x40000000
 231 #define RSTCTL_RSTERR           0x20000000
 232
 233 #define RSTCTL_SDEN             0x00000020
 234 #define RSTCTL_SDRST_B          0x00000040
 235 #define RSTCTL_PLLRST_B         0x00000080
 236
 237 #define TCALCR_CALRST_B         0x08000000
 238
 239 struct serdes_prctl_info {
 240         u32 id;
 241         u32 mask;
 242         u32 shift;
 243 };
 244
 245 struct serdes_prctl_info srds_prctl_info[] = {
 246 #ifdef CONFIG_SYS_FSL_SRDS_1
 247         {.id = 1,
 248          .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 249          .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
 250         },
 251
 252 #endif
 253 #ifdef CONFIG_SYS_FSL_SRDS_2
 254         {.id = 2,
 255          .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 256          .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
 257         },
 258 #endif
 259 #ifdef CONFIG_SYS_NXP_SRDS_3
 260         {.id = 3,
 261          .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 262          .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
 263         },
 264 #endif
 265         {} /* NULL ENTRY */
 266 };
 267
 268 static int get_serdes_prctl_info_idx(u32 serdes_id)
 269 {
 270         int pos = 0;
 271         struct serdes_prctl_info *srds_info;
 272
 273         /* loop until NULL ENTRY defined by .id=0 */
 274         for (srds_info = srds_prctl_info; srds_info->id != 0;
 275              srds_info++, pos++) {
 276                 if (srds_info->id == serdes_id)
 277                         return pos;
 278         }
 279
 280         return -1;
 281 }
 282
 283 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
 284                                    struct ccsr_serdes __iomem *serdes_base,
 285                                    bool cmplt)
 286 {
 287         int i, pos;
 288         u32 cfg_tmp;
 289
 290         pos = get_serdes_prctl_info_idx(serdes_id);
 291         if (pos == -1) {
 292                 printf("invalid serdes_id %d\n", serdes_id);
 293                 return;
 294         }
 295
 296         cfg_tmp = cfg & srds_prctl_info[pos].mask;
 297         cfg_tmp >>= srds_prctl_info[pos].shift;
 298
 299         for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
 300                 if (cmplt)
 301                         setbits_le32(&serdes_base->lane[i].gcr0,
 302                                      LNAGCR0_RT_RSTB);
 303                 else
 304                         clrbits_le32(&serdes_base->lane[i].gcr0,
 305                                      LNAGCR0_RT_RSTB);
 306         }
 307 }
 308
 309 static void do_pll_reset(u32 cfg,
 310                          struct ccsr_serdes __iomem *serdes_base)
 311 {
 312         int i;
 313
 314         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 315                 clrbits_le32(&serdes_base->bank[i].rstctl,
 316                              RSTCTL_RESET_MASK);
 317                 udelay(1);
 318
 319                 setbits_le32(&serdes_base->bank[i].rstctl,
 320                              RSTCTL_RSTREQ);
 321         }
 322         udelay(1);
 323 }
 324
 325 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
 326 {
 327         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 328         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 329 }
 330
 331 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
 332                                     struct ccsr_serdes __iomem *serdes_base)
 333 {
 334         if (!(cfg == 0x3 && i == 1)) {
 335                 udelay(1);
 336                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 337                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 338         }
 339         udelay(1);
 340 }
 341
 342 static void do_pll_reset_done(u32 cfg,
 343                               struct ccsr_serdes __iomem *serdes_base)
 344 {
 345         int i;
 346         u32 reg = 0;
 347
 348         for (i = 0; i < 2; i++) {
 349                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 350                 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
 351                         setbits_le32(&serdes_base->bank[i].rstctl,
 352                                      RSTCTL_RST_DONE);
 353                 }
 354         }
 355 }
 356
 357 static void do_serdes_enable(u32 cfg,
 358                              struct ccsr_serdes __iomem *serdes_base)
 359 {
 360         int i;
 361
 362         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 363                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
 364                 udelay(1);
 365
 366                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
 367                 udelay(1);
 368                 /* Take the Rx/Tx calibration out of reset */
 369                 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
 370         }
 371 }
 372
 373 static void do_pll_lock(u32 cfg,
 374                         struct ccsr_serdes __iomem *serdes_base)
 375 {
 376         int i;
 377         u32 reg = 0;
 378
 379         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 380                 /* if the PLL is not locked, set RST_ERR */
 381                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 382                 if (!((reg >> 23) & 0x1)) {
 383                         setbits_le32(&serdes_base->bank[i].rstctl,
 384                                      RSTCTL_RSTERR);
 385                 } else {
 386                         udelay(1);
 387                         setbits_le32(&serdes_base->bank[i].rstctl,
 388                                      RSTCTL_SDRST_B);
 389                         udelay(1);
 390                 }
 391         }
 392 }
 393
 394 int setup_serdes_volt(u32 svdd)
 395 {
 396         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 397         struct ccsr_serdes __iomem *serdes1_base =
 398                         (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
 399         u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
 400 #ifdef CONFIG_SYS_FSL_SRDS_2
 401         struct ccsr_serdes __iomem *serdes2_base =
 402                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
 403         u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 404 #endif
 405 #ifdef CONFIG_SYS_NXP_SRDS_3
 406         struct ccsr_serdes __iomem *serdes3_base =
 407                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
 408         u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 409 #endif
 410         u32 cfg_tmp;
 411         int svdd_cur, svdd_tar;
 412         int ret = 1;
 413
 414         /* Only support switch SVDD to 900mV */
 415         if (svdd != 900)
 416                 return -EINVAL;
 417
 418         /* Scale up to the LTC resolution is 1/4096V */
 419         svdd = (svdd * 4096) / 1000;
 420
 421         svdd_tar = svdd;
 422         svdd_cur = get_serdes_volt();
 423         if (svdd_cur < 0)
 424                 return -EINVAL;
 425
 426         debug("%s: current SVDD: %x; target SVDD: %x\n",
 427               __func__, svdd_cur, svdd_tar);
 428         if (svdd_cur == svdd_tar)
 429                 return 0;
 430
 431         /* Put the all enabled lanes in reset */
 432 #ifdef CONFIG_SYS_FSL_SRDS_1
 433         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
 434 #endif
 435
 436 #ifdef CONFIG_SYS_FSL_SRDS_2
 437         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
 438 #endif
 439 #ifdef CONFIG_SYS_NXP_SRDS_3
 440         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
 441 #endif
 442
 443         /* Put the all enabled PLL in reset */
 444 #ifdef CONFIG_SYS_FSL_SRDS_1
 445         cfg_tmp = cfg_rcwsrds1 & 0x3;
 446         do_pll_reset(cfg_tmp, serdes1_base);
 447 #endif
 448
 449 #ifdef CONFIG_SYS_FSL_SRDS_2
 450         cfg_tmp = cfg_rcwsrds1 & 0xC;
 451         cfg_tmp >>= 2;
 452         do_pll_reset(cfg_tmp, serdes2_base);
 453 #endif
 454
 455 #ifdef CONFIG_SYS_NXP_SRDS_3
 456         cfg_tmp = cfg_rcwsrds3 & 0x30;
 457         cfg_tmp >>= 4;
 458         do_pll_reset(cfg_tmp, serdes3_base);
 459 #endif
 460
 461         /* Put the Rx/Tx calibration into reset */
 462 #ifdef CONFIG_SYS_FSL_SRDS_1
 463         do_rx_tx_cal_reset(serdes1_base);
 464 #endif
 465
 466 #ifdef CONFIG_SYS_FSL_SRDS_2
 467         do_rx_tx_cal_reset(serdes2_base);
 468 #endif
 469
 470 #ifdef CONFIG_SYS_NXP_SRDS_3
 471         do_rx_tx_cal_reset(serdes3_base);
 472 #endif
 473
 474         ret = set_serdes_volt(svdd);
 475         if (ret < 0) {
 476                 printf("could not change SVDD\n");
 477                 ret = -1;
 478         }
 479
 480         /* For each PLL that’s not disabled via RCW enable the SERDES */
 481 #ifdef CONFIG_SYS_FSL_SRDS_1
 482         cfg_tmp = cfg_rcwsrds1 & 0x3;
 483         do_serdes_enable(cfg_tmp, serdes1_base);
 484 #endif
 485 #ifdef CONFIG_SYS_FSL_SRDS_2
 486         cfg_tmp = cfg_rcwsrds1 & 0xC;
 487         cfg_tmp >>= 2;
 488         do_serdes_enable(cfg_tmp, serdes2_base);
 489 #endif
 490 #ifdef CONFIG_SYS_NXP_SRDS_3
 491         cfg_tmp = cfg_rcwsrds3 & 0x30;
 492         cfg_tmp >>= 4;
 493         do_serdes_enable(cfg_tmp, serdes3_base);
 494 #endif
 495
 496         /* Wait for at at least 625us, ensure the PLLs being reset are locked */
 497         udelay(800);
 498
 499 #ifdef CONFIG_SYS_FSL_SRDS_1
 500         cfg_tmp = cfg_rcwsrds1 & 0x3;
 501         do_pll_lock(cfg_tmp, serdes1_base);
 502 #endif
 503
 504 #ifdef CONFIG_SYS_FSL_SRDS_2
 505         cfg_tmp = cfg_rcwsrds1 & 0xC;
 506         cfg_tmp >>= 2;
 507         do_pll_lock(cfg_tmp, serdes2_base);
 508 #endif
 509
 510 #ifdef CONFIG_SYS_NXP_SRDS_3
 511         cfg_tmp = cfg_rcwsrds3 & 0x30;
 512         cfg_tmp >>= 4;
 513         do_pll_lock(cfg_tmp, serdes3_base);
 514 #endif
 515
 516         /* Take the all enabled lanes out of reset */
 517 #ifdef CONFIG_SYS_FSL_SRDS_1
 518         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
 519 #endif
 520 #ifdef CONFIG_SYS_FSL_SRDS_2
 521         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
 522 #endif
 523
 524 #ifdef CONFIG_SYS_NXP_SRDS_3
 525         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
 526 #endif
 527
 528         /* For each PLL being reset, and achieved PLL lock set RST_DONE */
 529 #ifdef CONFIG_SYS_FSL_SRDS_1
 530         cfg_tmp = cfg_rcwsrds1 & 0x3;
 531         do_pll_reset_done(cfg_tmp, serdes1_base);
 532 #endif
 533 #ifdef CONFIG_SYS_FSL_SRDS_2
 534         cfg_tmp = cfg_rcwsrds1 & 0xC;
 535         cfg_tmp >>= 2;
 536         do_pll_reset_done(cfg_tmp, serdes2_base);
 537 #endif
 538
 539 #ifdef CONFIG_SYS_NXP_SRDS_3
 540         cfg_tmp = cfg_rcwsrds3 & 0x30;
 541         cfg_tmp >>= 4;
 542         do_pll_reset_done(cfg_tmp, serdes3_base);
 543 #endif
 544
 545         return ret;
 546 }
 547
 548 void fsl_serdes_init(void)
 549 {
 550 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 551         int i , j;
 552
 553 #ifdef CONFIG_ARCH_LX2160A
 554         for (i = XFI1, j = 1; i <= XFI14; i++, j++)
 555                 xfi_dpmac[i] = j;
 556
 557         for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
 558                 sgmii_dpmac[i] = j;
 559
 560         for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
 561                 a25gaui_dpmac[i] = j;
 562
 563         for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
 564                 xlaui_dpmac[i] = j;
 565
 566         for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
 567                 caui2_dpmac[i] = j;
 568
 569         for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
 570                 caui4_dpmac[i] = j;
 571 #else
 572         for (i = XFI1, j = 1; i <= XFI8; i++, j++)
 573                 xfi_dpmac[i] = j;
 574
 575         for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
 576                 sgmii_dpmac[i] = j;
 577 #endif
 578 #endif
 579
 580 #ifdef CONFIG_SYS_FSL_SRDS_1
 581         serdes_init(FSL_SRDS_1,
 582                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
 583                     FSL_CHASSIS3_SRDS1_REGSR,
 584                     FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 585                     FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
 586                     serdes1_prtcl_map);
 587 #endif
 588 #ifdef CONFIG_SYS_FSL_SRDS_2
 589         serdes_init(FSL_SRDS_2,
 590                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 591                     FSL_CHASSIS3_SRDS2_REGSR,
 592                     FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 593                     FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
 594                     serdes2_prtcl_map);
 595 #endif
 596 #ifdef CONFIG_SYS_NXP_SRDS_3
 597         serdes_init(NXP_SRDS_3,
 598                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
 599                     FSL_CHASSIS3_SRDS3_REGSR,
 600                     FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 601                     FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
 602                     serdes3_prtcl_map);
 603 #endif
 604 }
 605
 606 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
 607 {
 608         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 609         char scfg[16], snum[16];
 610         int cfgr = 0;
 611         u32 cfg;
 612
 613         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 614         cfg >>= sd_prctl_shift;
 615         cfg = serdes_get_number(sd, cfg);
 616
 617 #if defined(SRDS_BITS_PER_LANE)
 618         /*
 619          * reverse lanes, lane 0 should be printed first so it must be moved to
 620          * high order bits.
 621          * For example bb58 should read 85bb, lane 0 being protocol 8.
 622          * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
 623          * independent per-lane protocol configuration, at this time LS1028A and
 624          * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
 625          * lanes as a single value.
 626          */
 627         for (int i = 0; i < SRDS_MAX_LANES; i++) {
 628                 int tmp;
 629
 630                 tmp = cfg >> (i * SRDS_BITS_PER_LANE);
 631                 tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
 632                 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
 633                 cfgr |= tmp;
 634         }
 635 #endif /* SRDS_BITS_PER_LANE */
 636
 637         snprintf(snum, 16, "serdes%d", sd);
 638         snprintf(scfg, 16, "%x", cfgr);
 639         env_set(snum, scfg);
 640
 641         return 0;
 642 }
 643
 644 int serdes_misc_init(void)
 645 {
 646 #ifdef CONFIG_SYS_FSL_SRDS_1
 647         serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
 648                        FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 649                        FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
 650 #endif
 651 #ifdef CONFIG_SYS_FSL_SRDS_2
 652         serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
 653                        FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 654                        FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
 655 #endif
 656 #ifdef CONFIG_SYS_NXP_SRDS_3
 657         serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
 658                        FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 659                        FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
 660 #endif
 661
 662         return 0;
 663 }