4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
28 select SYS_FSL_HAS_CCI400
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5
40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F
43 select SYS_I2C_MXC_I2C1
44 select SYS_I2C_MXC_I2C2
45 select SYS_I2C_MXC_I2C3
46 select SYS_I2C_MXC_I2C4
47 select SYS_I2C_MXC_I2C5
48 select SYS_I2C_MXC_I2C6
49 select SYS_I2C_MXC_I2C7
50 select SYS_I2C_MXC_I2C8
51 select SYS_FSL_ERRATUM_A009007
52 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
53 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
54 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
59 select ARMV8_SET_SMPEN
60 select ARM_ERRATA_855873 if !TFABOOT
67 select SYS_FSL_DDR_VER_50
68 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
69 select SYS_FSL_ERRATUM_A008997
70 select SYS_FSL_ERRATUM_A009007
71 select SYS_FSL_ERRATUM_A009008
72 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
73 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
74 select SYS_FSL_ERRATUM_A009798
75 select SYS_FSL_ERRATUM_A009929
76 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
77 select SYS_FSL_ERRATUM_A010315
78 select SYS_FSL_ERRATUM_A010539
79 select SYS_FSL_HAS_DDR3
80 select SYS_FSL_HAS_DDR4
81 select ARCH_EARLY_INIT_R
82 select BOARD_EARLY_INIT_F
84 select SYS_I2C_MXC_I2C1
85 select SYS_I2C_MXC_I2C2
86 select SYS_I2C_MXC_I2C3
87 select SYS_I2C_MXC_I2C4
92 select ARMV8_SET_SMPEN
99 select SYS_FSL_DDR_VER_50
100 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
101 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
102 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
103 select SYS_FSL_ERRATUM_A008997
104 select SYS_FSL_ERRATUM_A009007
105 select SYS_FSL_ERRATUM_A009008
106 select SYS_FSL_ERRATUM_A009798
107 select SYS_FSL_ERRATUM_A009801
108 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
109 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
110 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
111 select SYS_FSL_ERRATUM_A010539
112 select SYS_FSL_HAS_DDR4
113 select SYS_FSL_SRDS_2
114 select ARCH_EARLY_INIT_R
115 select BOARD_EARLY_INIT_F
117 select SYS_I2C_MXC_I2C1
118 select SYS_I2C_MXC_I2C2
119 select SYS_I2C_MXC_I2C3
120 select SYS_I2C_MXC_I2C4
126 select ARMV8_SET_SMPEN
127 select ARM_ERRATA_855873 if !TFABOOT
128 select FSL_LAYERSCAPE
130 select SYS_FSL_SRDS_1
131 select SYS_HAS_SERDES
133 select SYS_FSL_DDR_LE
134 select SYS_FSL_DDR_VER_50
137 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
138 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
139 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
140 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
141 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
142 select SYS_FSL_ERRATUM_A009007
143 select SYS_FSL_HAS_CCI400
144 select SYS_FSL_HAS_DDR4
145 select SYS_FSL_HAS_RGMII
146 select SYS_FSL_HAS_SEC
147 select SYS_FSL_SEC_COMPAT_5
148 select SYS_FSL_SEC_LE
149 select SYS_FSL_SRDS_1
150 select SYS_FSL_SRDS_2
153 select FSL_TZPC_BP147
154 select ARCH_EARLY_INIT_R
155 select BOARD_EARLY_INIT_F
157 select SYS_I2C_MXC_I2C1
158 select SYS_I2C_MXC_I2C2
159 select SYS_I2C_MXC_I2C3
160 select SYS_I2C_MXC_I2C4
166 select ARMV8_SET_SMPEN
167 select ARM_ERRATA_826974
168 select ARM_ERRATA_828024
169 select ARM_ERRATA_829520
170 select ARM_ERRATA_833471
171 select FSL_LAYERSCAPE
173 select SYS_FSL_SRDS_1
174 select SYS_HAS_SERDES
176 select SYS_FSL_DDR_LE
177 select SYS_FSL_DDR_VER_50
178 select SYS_FSL_HAS_CCN504
179 select SYS_FSL_HAS_DP_DDR
180 select SYS_FSL_HAS_SEC
181 select SYS_FSL_HAS_DDR4
182 select SYS_FSL_SEC_COMPAT_5
183 select SYS_FSL_SEC_LE
184 select SYS_FSL_SRDS_2
188 select FSL_TZPC_BP147
189 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
190 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
191 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
192 select SYS_FSL_ERRATUM_A008585
193 select SYS_FSL_ERRATUM_A008997
194 select SYS_FSL_ERRATUM_A009007
195 select SYS_FSL_ERRATUM_A009008
196 select SYS_FSL_ERRATUM_A009635
197 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
198 select SYS_FSL_ERRATUM_A009798
199 select SYS_FSL_ERRATUM_A009801
200 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
201 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
202 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
203 select SYS_FSL_ERRATUM_A009203
204 select ARCH_EARLY_INIT_R
205 select BOARD_EARLY_INIT_F
207 select SYS_I2C_MXC_I2C1
208 select SYS_I2C_MXC_I2C2
209 select SYS_I2C_MXC_I2C3
210 select SYS_I2C_MXC_I2C4
211 imply DISTRO_DEFAULTS
216 select ARMV8_SET_SMPEN
219 select SYS_HAS_SERDES
220 select SYS_FSL_SRDS_1
221 select SYS_FSL_SRDS_2
222 select SYS_NXP_SRDS_3
224 select SYS_FSL_DDR_LE
225 select SYS_FSL_DDR_VER_50
228 select SYS_FSL_HAS_RGMII
229 select SYS_FSL_HAS_SEC
230 select SYS_FSL_HAS_CCN508
231 select SYS_FSL_HAS_DDR4
232 select SYS_FSL_SEC_COMPAT_5
233 select SYS_FSL_SEC_LE
234 select ARCH_EARLY_INIT_R
235 select BOARD_EARLY_INIT_F
237 select SYS_I2C_MXC_I2C1
238 select SYS_I2C_MXC_I2C2
239 select SYS_I2C_MXC_I2C3
240 select SYS_I2C_MXC_I2C4
241 select SYS_I2C_MXC_I2C5
242 select SYS_I2C_MXC_I2C6
243 select SYS_I2C_MXC_I2C7
244 select SYS_I2C_MXC_I2C8
245 imply DISTRO_DEFAULTS
252 select SYS_FSL_HAS_CCI400
253 select SYS_FSL_HAS_SEC
254 select SYS_FSL_SEC_COMPAT_5
255 select SYS_FSL_SEC_BE
264 bool "Management Complex network"
265 depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
269 Enable Management Complex (MC) network
271 menu "Layerscape architecture"
272 depends on FSL_LSCH2 || FSL_LSCH3
274 config FSL_LAYERSCAPE
277 config FSL_PCIE_COMPAT
278 string "PCIe compatible of Kernel DT"
279 depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
280 default "fsl,ls1012a-pcie" if ARCH_LS1012A
281 default "fsl,ls1028a-pcie" if ARCH_LS1028A
282 default "fsl,ls1043a-pcie" if ARCH_LS1043A
283 default "fsl,ls1046a-pcie" if ARCH_LS1046A
284 default "fsl,ls2080a-pcie" if ARCH_LS2080A
285 default "fsl,ls1088a-pcie" if ARCH_LS1088A
286 default "fsl,lx2160a-pcie" if ARCH_LX2160A
288 This compatible is used to find pci controller node in Kernel DT
291 config HAS_FEATURE_GIC64K_ALIGN
293 default y if ARCH_LS1043A
295 config HAS_FEATURE_ENHANCED_MSI
297 default y if ARCH_LS1043A
299 menu "Layerscape PPA"
301 bool "FSL Layerscape PPA firmware support"
302 depends on !ARMV8_PSCI
303 select ARMV8_SEC_FIRMWARE_SUPPORT
304 select SEC_FIRMWARE_ARMV8_PSCI
305 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
307 The FSL Primary Protected Application (PPA) is a software component
308 which is loaded during boot stage, and then remains resident in RAM
309 and runs in the TrustZone after boot.
312 config SPL_FSL_LS_PPA
313 bool "FSL Layerscape PPA firmware support for SPL build"
314 depends on !ARMV8_PSCI
315 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
316 select SEC_FIRMWARE_ARMV8_PSCI
317 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
319 The FSL Primary Protected Application (PPA) is a software component
320 which is loaded during boot stage, and then remains resident in RAM
321 and runs in the TrustZone after boot. This is to load PPA during SPL
322 stage instead of the RAM version of U-Boot. Once PPA is initialized,
323 the rest of U-Boot (including RAM version) runs at EL2.
325 prompt "FSL Layerscape PPA firmware loading-media select"
326 depends on FSL_LS_PPA
327 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
328 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
329 default SYS_LS_PPA_FW_IN_XIP
331 config SYS_LS_PPA_FW_IN_XIP
334 Say Y here if the PPA firmware locate at XIP flash, such
335 as NOR or QSPI flash.
337 config SYS_LS_PPA_FW_IN_MMC
338 bool "eMMC or SD Card"
340 Say Y here if the PPA firmware locate at eMMC/SD card.
342 config SYS_LS_PPA_FW_IN_NAND
345 Say Y here if the PPA firmware locate at NAND flash.
349 config LS_PPA_ESBC_HDR_SIZE
350 hex "Length of PPA ESBC header"
351 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
354 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
355 NAND to memory to validate PPA image.
359 config SYS_FSL_ERRATUM_A008997
360 bool "Workaround for USB PHY erratum A008997"
362 config SYS_FSL_ERRATUM_A009007
365 Workaround for USB PHY erratum A009007
367 config SYS_FSL_ERRATUM_A009008
368 bool "Workaround for USB PHY erratum A009008"
370 config SYS_FSL_ERRATUM_A009798
371 bool "Workaround for USB PHY erratum A009798"
373 config SYS_FSL_ERRATUM_A010315
374 bool "Workaround for PCIe erratum A010315"
376 config SYS_FSL_ERRATUM_A010539
377 bool "Workaround for PIN MUX erratum A010539"
380 int "Maximum number of CPUs permitted for Layerscape"
381 default 2 if ARCH_LS1028A
382 default 4 if ARCH_LS1043A
383 default 4 if ARCH_LS1046A
384 default 16 if ARCH_LS2080A
385 default 8 if ARCH_LS1088A
386 default 16 if ARCH_LX2160A
389 Set this number to the maximum number of possible CPUs in the SoC.
390 SoCs may have multiple clusters with each cluster may have multiple
391 ports. If some ports are reserved but higher ports are used for
392 cores, count the reserved ports. This will allocate enough memory
393 in spin table to properly handle all cores.
396 bool "Fan controller"
398 Enable the EMC2305 fan controller for configuration of fan
404 Enable Freescale Secure Boot feature
407 bool "Init the QSPI AHB bus"
409 The default setting for QSPI AHB bus just support 3bytes addressing.
410 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
411 bus for those flashes to support the full QSPI flash size.
413 config SYS_CCI400_OFFSET
414 hex "Offset for CCI400 base"
415 depends on SYS_FSL_HAS_CCI400
416 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
417 default 0x180000 if FSL_LSCH2
419 Offset for CCI400 base
420 CCI400 base addr = CCSRBAR + CCI400_OFFSET
422 config SYS_FSL_IFC_BANK_COUNT
423 int "Maximum banks of Integrated flash controller"
424 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
425 default 4 if ARCH_LS1043A
426 default 4 if ARCH_LS1046A
427 default 8 if ARCH_LS2080A || ARCH_LS1088A
429 config SYS_FSL_HAS_CCI400
432 config SYS_FSL_HAS_CCN504
435 config SYS_FSL_HAS_CCN508
438 config SYS_FSL_HAS_DP_DDR
441 config SYS_FSL_SRDS_1
444 config SYS_FSL_SRDS_2
447 config SYS_NXP_SRDS_3
450 config SYS_HAS_SERDES
462 config FSL_TZPC_BP147
466 menu "Layerscape clock tree configuration"
467 depends on FSL_LSCH2 || FSL_LSCH3
470 bool "Enable clock tree initialization"
473 config CLUSTER_CLK_FREQ
474 int "Reference clock of core cluster"
475 depends on ARCH_LS1012A
478 This number is the reference clock frequency of core PLL.
479 For most platforms, the core PLL and Platform PLL have the same
480 reference clock, but for some platforms, LS1012A for instance,
481 they are provided sepatately.
483 config SYS_FSL_PCLK_DIV
484 int "Platform clock divider"
485 default 1 if ARCH_LS1028A
486 default 1 if ARCH_LS1043A
487 default 1 if ARCH_LS1046A
488 default 1 if ARCH_LS1088A
491 This is the divider that is used to derive Platform clock from
492 Platform PLL, in another word:
493 Platform_clk = Platform_PLL_freq / this_divider
495 config SYS_FSL_DSPI_CLK_DIV
496 int "DSPI clock divider"
497 default 1 if ARCH_LS1043A
500 This is the divider that is used to derive DSPI clock from Platform
501 clock, in another word DSPI_clk = Platform_clk / this_divider.
503 config SYS_FSL_DUART_CLK_DIV
504 int "DUART clock divider"
505 default 1 if ARCH_LS1043A
506 default 4 if ARCH_LX2160A
509 This is the divider that is used to derive DUART clock from Platform
510 clock, in another word DUART_clk = Platform_clk / this_divider.
512 config SYS_FSL_I2C_CLK_DIV
513 int "I2C clock divider"
514 default 1 if ARCH_LS1043A
517 This is the divider that is used to derive I2C clock from Platform
518 clock, in another word I2C_clk = Platform_clk / this_divider.
520 config SYS_FSL_IFC_CLK_DIV
521 int "IFC clock divider"
522 default 1 if ARCH_LS1043A
525 This is the divider that is used to derive IFC clock from Platform
526 clock, in another word IFC_clk = Platform_clk / this_divider.
528 config SYS_FSL_LPUART_CLK_DIV
529 int "LPUART clock divider"
530 default 1 if ARCH_LS1043A
533 This is the divider that is used to derive LPUART clock from Platform
534 clock, in another word LPUART_clk = Platform_clk / this_divider.
536 config SYS_FSL_SDHC_CLK_DIV
537 int "SDHC clock divider"
538 default 1 if ARCH_LS1043A
539 default 1 if ARCH_LS1012A
542 This is the divider that is used to derive SDHC clock from Platform
543 clock, in another word SDHC_clk = Platform_clk / this_divider.
545 config SYS_FSL_QMAN_CLK_DIV
546 int "QMAN clock divider"
547 default 1 if ARCH_LS1043A
550 This is the divider that is used to derive QMAN clock from Platform
551 clock, in another word QMAN_clk = Platform_clk / this_divider.
557 Reserve memory from the top, tracked by gd->arch.resv_ram. This
558 reserved RAM can be used by special driver that resides in memory
559 after U-Boot exits. It's up to implementation to allocate and allow
560 access to this reserved memory. For example, the reserved RAM can
561 be at the high end of physical memory. The reserve RAM may be
562 excluded from memory bank(s) passed to OS, or marked as reserved.
567 Ethernet controller 1, this is connected to
568 MAC17 for LX2160A or to MAC3 for other SoCs
569 Provides DPAA2 capabilities
574 Ethernet controller 2, this is connected to
575 MAC18 for LX2160A or to MAC4 for other SoCs
576 Provides DPAA2 capabilities
578 config SYS_FSL_ERRATUM_A008336
581 config SYS_FSL_ERRATUM_A008514
584 config SYS_FSL_ERRATUM_A008585
587 config SYS_FSL_ERRATUM_A008850
590 config SYS_FSL_ERRATUM_A009203
593 config SYS_FSL_ERRATUM_A009635
596 config SYS_FSL_ERRATUM_A009660
599 config SYS_FSL_ERRATUM_A009929
603 config SYS_FSL_HAS_RGMII
605 depends on SYS_FSL_EC1 || SYS_FSL_EC2
608 config SYS_MC_RSV_MEM_ALIGN
609 hex "Management Complex reserved memory alignment"
611 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
613 Reserved memory needs to be aligned for MC to use. Default value
617 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
619 config HAS_FSL_XHCI_USB
621 default y if ARCH_LS1043A || ARCH_LS1046A
623 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
624 pins, select it when the pins are assigned to USB.
627 bool "Support for booting from TFA"
630 Enabling this will make a U-Boot binary that is capable of being