arch/arm/cpu/armv7/ls102xa/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <log.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <asm/arch/ls102xa_soc.h>
  13 #include <asm/arch/ls102xa_stream_id.h>
  14 #include <fsl_csu.h>
  15 #include <fsl_ddr_sdram.h>
  16
  17 struct liodn_id_table sec_liodn_tbl[] = {
  18         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  19         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  20         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  21         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  22         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  23         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  24         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  25         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  26         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  27         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  28         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  29         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  30         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  31         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  32         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  33         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  34 };
  35
  36 struct smmu_stream_id dev_stream_id[] = {
  37         { 0x100, 0x01, "ETSEC MAC1" },
  38         { 0x104, 0x02, "ETSEC MAC2" },
  39         { 0x108, 0x03, "ETSEC MAC3" },
  40         { 0x10c, 0x04, "PEX1" },
  41         { 0x110, 0x05, "PEX2" },
  42         { 0x114, 0x06, "qDMA" },
  43         { 0x118, 0x07, "SATA" },
  44         { 0x11c, 0x08, "USB3" },
  45         { 0x120, 0x09, "QE" },
  46         { 0x124, 0x0a, "eSDHC" },
  47         { 0x128, 0x0b, "eMA" },
  48         { 0x14c, 0x0c, "2D-ACE" },
  49         { 0x150, 0x0d, "USB2" },
  50         { 0x18c, 0x0e, "DEBUG" },
  51 };
  52
  53 unsigned int get_soc_major_rev(void)
  54 {
  55         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  56         unsigned int svr, major;
  57
  58         svr = in_be32(&gur->svr);
  59         major = SVR_MAJ(svr);
  60
  61         return major;
  62 }
  63
  64 static void erratum_a009008(void)
  65 {
  66 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  67         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  68
  69         clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  70                         0xF << 6,
  71                         SCFG_USB_TXVREFTUNE << 6);
  72 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  73 }
  74
  75 static void erratum_a009798(void)
  76 {
  77 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  78         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  79
  80         clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  81                         SCFG_USB_SQRXTUNE_MASK << 23);
  82 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  83 }
  84
  85 static void erratum_a008997(void)
  86 {
  87 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  88         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  89
  90         clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
  91                         SCFG_USB_PCSTXSWINGFULL_MASK,
  92                         SCFG_USB_PCSTXSWINGFULL_VAL);
  93 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  94 }
  95
  96 static void erratum_a009007(void)
  97 {
  98 #ifdef CONFIG_SYS_FSL_ERRATUM_A009007
  99         void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
 100
 101         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
 102         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
 103         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
 104         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
 105 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
 106 }
 107
 108 static void erratum_a008850_early(void)
 109 {
 110 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 111         /* part 1 of 2 */
 112         struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 113                                                 CONFIG_SYS_CCI400_OFFSET);
 114         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 115
 116         /* disables propagation of barrier transactions to DDRC from CCI400 */
 117         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 118
 119         /* disable the re-ordering in DDRC */
 120         out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 121 #endif
 122 }
 123
 124 void erratum_a008850_post(void)
 125 {
 126 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 127         /* part 2 of 2 */
 128         struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 129                                                 CONFIG_SYS_CCI400_OFFSET);
 130         struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 131         u32 tmp;
 132
 133         /* enable propagation of barrier transactions to DDRC from CCI400 */
 134         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 135
 136         /* enable the re-ordering in DDRC */
 137         tmp = in_be32(&ddr->eor);
 138         tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 139         out_be32(&ddr->eor, tmp);
 140 #endif
 141 }
 142
 143 void s_init(void)
 144 {
 145 }
 146
 147 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 148 void erratum_a010315(void)
 149 {
 150         int i;
 151
 152         for (i = PCIE1; i <= PCIE2; i++)
 153                 if (!is_serdes_configured(i)) {
 154                         debug("PCIe%d: disabled all R/W permission!\n", i);
 155                         set_pcie_ns_access(i, 0);
 156                 }
 157 }
 158 #endif
 159
 160 int arch_soc_init(void)
 161 {
 162         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 163         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 164                                         CONFIG_SYS_CCI400_OFFSET);
 165         unsigned int major;
 166
 167 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 168         enable_layerscape_ns_access();
 169 #endif
 170
 171 #ifdef CONFIG_FSL_QSPI
 172         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 173 #endif
 174
 175 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 176         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 177 #endif
 178
 179         /* Configure Little endian for SAI, ASRC and SPDIF */
 180         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 181
 182         /*
 183          * Enable snoop requests and DVM message requests for
 184          * All the slave insterfaces.
 185          */
 186         out_le32(&cci->slave[0].snoop_ctrl,
 187                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 188         out_le32(&cci->slave[1].snoop_ctrl,
 189                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 190         out_le32(&cci->slave[2].snoop_ctrl,
 191                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 192         out_le32(&cci->slave[4].snoop_ctrl,
 193                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 194
 195         major = get_soc_major_rev();
 196         if (major == SOC_MAJOR_VER_1_0) {
 197                 /*
 198                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 199                  * Register All transactions are treated as non-shareable
 200                  */
 201                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 202                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 203         }
 204
 205         /* Enable all the snoop signal for various masters */
 206         out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
 207                                 SCFG_SNPCNFGCR_DCU_RD_WR |
 208                                 SCFG_SNPCNFGCR_SATA_RD_WR |
 209                                 SCFG_SNPCNFGCR_USB3_RD_WR |
 210                                 SCFG_SNPCNFGCR_DBG_RD_WR |
 211                                 SCFG_SNPCNFGCR_EDMA_SNP);
 212
 213         /*
 214          * Memory controller require a register write before being enabled.
 215          * Affects: DDR
 216          * Register: EDDRTQCFG
 217          * Description: Memory controller performance is not optimal with
 218          *              default internal target queue register values.
 219          * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
 220          */
 221         out_be32(&scfg->eddrtqcfg, 0x63b20042);
 222
 223         /* Erratum */
 224         erratum_a008850_early();
 225         erratum_a009008();
 226         erratum_a009798();
 227         erratum_a008997();
 228         erratum_a009007();
 229
 230         return 0;
 231 }
 232
 233 int ls102xa_smmu_stream_id_init(void)
 234 {
 235         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 236                                       ARRAY_SIZE(sec_liodn_tbl));
 237
 238         ls102xa_config_smmu_stream_id(dev_stream_id,
 239                                       ARRAY_SIZE(dev_stream_id));
 240
 241         return 0;
 242 }