arch/arm/cpu/armv7/ls102xa/fdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <linux/libfdt.h>
   8 #include <fdt_support.h>
   9 #include <asm/io.h>
  10 #include <asm/processor.h>
  11 #include <asm/arch/clock.h>
  12 #include <linux/ctype.h>
  13 #ifdef CONFIG_FSL_ESDHC
  14 #include <fsl_esdhc.h>
  15 #endif
  16 #include <tsec.h>
  17 #include <asm/arch/immap_ls102xa.h>
  18 #include <fsl_sec.h>
  19 #include <dm.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 void ft_fixup_enet_phy_connect_type(void *fdt)
  24 {
  25 #ifdef CONFIG_DM_ETH
  26         struct udevice *dev;
  27 #else
  28         struct eth_device *dev;
  29 #endif
  30         struct tsec_private *priv;
  31         const char *enet_path, *phy_path;
  32         char enet[16];
  33         char phy[16];
  34         int phy_node;
  35         int i = 0;
  36         uint32_t ph;
  37 #ifdef CONFIG_DM_ETH
  38         char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
  39                           "ethernet@2d90000" };
  40 #else
  41         char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
  42 #endif
  43
  44         for (; i < ARRAY_SIZE(name); i++) {
  45                 dev = eth_get_dev_by_name(name[i]);
  46                 if (dev) {
  47                         sprintf(enet, "ethernet%d", i);
  48                         sprintf(phy, "enet%d_rgmii_phy", i);
  49                 } else {
  50                         continue;
  51                 }
  52
  53                 priv = dev->priv;
  54                 if (priv->flags & TSEC_SGMII)
  55                         continue;
  56
  57                 enet_path = fdt_get_alias(fdt, enet);
  58                 if (!enet_path)
  59                         continue;
  60
  61                 phy_path = fdt_get_alias(fdt, phy);
  62                 if (!phy_path)
  63                         continue;
  64
  65                 phy_node = fdt_path_offset(fdt, phy_path);
  66                 if (phy_node < 0)
  67                         continue;
  68
  69                 ph = fdt_create_phandle(fdt, phy_node);
  70                 if (ph)
  71                         do_fixup_by_path_u32(fdt, enet_path,
  72                                              "phy-handle", ph, 1);
  73
  74                 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  75                                  phy_string_for_interface(
  76                                  PHY_INTERFACE_MODE_RGMII_ID),
  77                                  strlen(phy_string_for_interface(
  78                                  PHY_INTERFACE_MODE_RGMII_ID)) + 1,
  79                                  1);
  80         }
  81 }
  82
  83 void ft_cpu_setup(void *blob, bd_t *bd)
  84 {
  85         int off;
  86         int val;
  87         const char *sysclk_path;
  88         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  89         unsigned int svr;
  90         svr = in_be32(&gur->svr);
  91
  92         unsigned long busclk = get_bus_freq(0);
  93
  94         /* delete crypto node if not on an E-processor */
  95         if (!IS_E_PROCESSOR(svr))
  96                 fdt_fixup_crypto_node(blob, 0);
  97 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  98         else {
  99                 ccsr_sec_t __iomem *sec;
 100
 101                 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 102                 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 103         }
 104 #endif
 105
 106         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 107         while (off != -FDT_ERR_NOTFOUND) {
 108                 val = gd->cpu_clk;
 109                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 110                 off = fdt_node_offset_by_prop_value(blob, off,
 111                                                     "device_type", "cpu", 4);
 112         }
 113
 114         do_fixup_by_prop_u32(blob, "device_type", "soc",
 115                              4, "bus-frequency", busclk, 1);
 116
 117         ft_fixup_enet_phy_connect_type(blob);
 118
 119 #ifdef CONFIG_SYS_NS16550
 120         do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
 121                                "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 122 #endif
 123
 124         sysclk_path = fdt_get_alias(blob, "sysclk");
 125         if (sysclk_path)
 126                 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
 127                                      CONFIG_SYS_CLK_FREQ, 1);
 128         do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
 129                                "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 130
 131 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 132 #define UBOOT_HEAD_LEN  0x1000
 133         /*
 134          * Reserved memory in SD boot deep sleep case.
 135          * Second stage uboot binary and malloc space should be reserved.
 136          * If the memory they occupied has not been reserved, then this
 137          * space would be used by kernel and overwritten in uboot when
 138          * deep sleep resume, which cause deep sleep failed.
 139          * Since second uboot binary has a head, that space need to be
 140          * reserved either(assuming its size is less than 0x1000).
 141          */
 142         off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
 143                         CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
 144                         UBOOT_HEAD_LEN);
 145         if (off < 0)
 146                 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
 147                        fdt_strerror(off));
 148 #endif
 149
 150 #if defined(CONFIG_FSL_ESDHC)
 151         fdt_fixup_esdhc(blob, bd);
 152 #endif
 153
 154         /*
 155          * platform bus clock = system bus clock/2
 156          * Here busclk = system bus clock
 157          * We are using the platform bus clock as 1588 Timer reference
 158          * clock source select
 159          */
 160         do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
 161                                "timer-frequency", busclk / 2, 1);
 162
 163         /*
 164          * clock-freq should change to clock-frequency and
 165          * flexcan-v1.0 should change to p1010-flexcan respectively
 166          * in the future.
 167          */
 168         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 169                                "clock_freq", busclk / 2, 1);
 170
 171         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 172                                "clock-frequency", busclk / 2, 1);
 173
 174         do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
 175                                "clock-frequency", busclk / 2, 1);
 176
 177 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 178         off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 179                                             CONFIG_SYS_IFC_ADDR);
 180         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 181 #else
 182         off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
 183                                             QSPI0_BASE_ADDR);
 184         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 185         off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
 186                                             DSPI1_BASE_ADDR);
 187         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 188 #endif
 189 }