arch/arm/cpu/armv7/keystone/ddr3.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <asm/io.h>
  11 #include <common.h>
  12 #include <asm/arch/ddr3.h>
  13
  14 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
  15 {
  16         unsigned int tmp;
  17
  18         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
  19                  & 0x00000001) != 0x00000001)
  20                 ;
  21
  22         __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
  23
  24         tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
  25         tmp &= ~(phy_cfg->pgcr1_mask);
  26         tmp |= phy_cfg->pgcr1_val;
  27         __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
  28
  29         __raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);
  30         __raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);
  31         __raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);
  32         __raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);
  33
  34         tmp =  __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
  35         tmp &= ~(phy_cfg->dcr_mask);
  36         tmp |= phy_cfg->dcr_val;
  37         __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
  38
  39         __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
  40         __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
  41         __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
  42         __raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
  43         __raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
  44         __raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
  45         __raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
  46         __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
  47
  48         __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
  49         __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
  50         __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
  51
  52         __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
  53         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  54                 ;
  55
  56         __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
  57         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  58                 ;
  59 }
  60
  61 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
  62 {
  63         __raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
  64         __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
  65         __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
  66         __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
  67         __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
  68         __raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
  69         __raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
  70 }
  71
  72 void ddr3_reset_ddrphy(void)
  73 {
  74         u32 tmp;
  75
  76         /* Assert DDR3A  PHY reset */
  77         tmp = readl(KS2_DDR3APLLCTL1);
  78         tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
  79         writel(tmp, KS2_DDR3APLLCTL1);
  80
  81         /* wait 10us to catch the reset */
  82         udelay(10);
  83
  84         /* Release DDR3A PHY reset */
  85         tmp = readl(KS2_DDR3APLLCTL1);
  86         tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
  87         __raw_writel(tmp, KS2_DDR3APLLCTL1);
  88 }