1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
4 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/mach-imx/sys_proto.h>
18 #include <asm/arch/mxcmmc.h>
22 * get the system pll clock in Hz
24 * mfi + mfn / (mfd +1)
25 * f = 2 * f_ref * --------------------
28 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
30 unsigned int mfi = (pll >> 10) & 0xf;
31 unsigned int mfn = pll & 0x3ff;
32 unsigned int mfd = (pll >> 16) & 0x3ff;
33 unsigned int pd = (pll >> 26) & 0xf;
35 mfi = mfi <= 5 ? 5 : mfi;
37 return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
38 (mfd + 1) * (pd + 1));
41 static ulong clk_in_32k(void)
43 return 1024 * CONFIG_MX27_CLK32;
46 static ulong clk_in_26m(void)
48 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
50 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
52 return 26000000 * 2 / 3;
58 static ulong imx_get_mpllclk(void)
60 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
61 ulong cscr = readl(&pll->cscr);
64 if (cscr & CSCR_MCU_SEL)
69 return imx_decode_pll(readl(&pll->mpctl0), fref);
72 static ulong imx_get_armclk(void)
74 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
75 ulong cscr = readl(&pll->cscr);
76 ulong fref = imx_get_mpllclk();
79 if (!(cscr & CSCR_ARM_SRC_MPLL))
80 fref = lldiv((fref * 2), 3);
82 div = ((cscr >> 12) & 0x3) + 1;
84 return lldiv(fref, div);
87 static ulong imx_get_ahbclk(void)
89 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
90 ulong cscr = readl(&pll->cscr);
91 ulong fref = imx_get_mpllclk();
94 div = ((cscr >> 8) & 0x3) + 1;
96 return lldiv(fref * 2, 3 * div);
99 static __attribute__((unused)) ulong imx_get_spllclk(void)
101 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
102 ulong cscr = readl(&pll->cscr);
105 if (cscr & CSCR_SP_SEL)
110 return imx_decode_pll(readl(&pll->spctl0), fref);
113 static ulong imx_decode_perclk(ulong div)
115 return lldiv((imx_get_mpllclk() * 2), (div * 3));
118 static ulong imx_get_perclk1(void)
120 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
122 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
125 static ulong imx_get_perclk2(void)
127 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
129 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
132 static __attribute__((unused)) ulong imx_get_perclk3(void)
134 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
136 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
139 static __attribute__((unused)) ulong imx_get_perclk4(void)
141 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
143 return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
146 unsigned int mxc_get_clock(enum mxc_clock clk)
150 return imx_get_armclk();
152 return imx_get_ahbclk()/2;
154 return imx_get_perclk1();
156 return imx_get_ahbclk();
158 return imx_get_perclk2();
164 u32 get_cpu_rev(void)
166 return MXC_CPU_MX27 << 12;
169 #if defined(CONFIG_DISPLAY_CPUINFO)
170 int print_cpuinfo (void)
174 printf("CPU: Freescale i.MX27 at %s MHz\n\n",
175 strmhz(buf, imx_get_mpllclk()));
180 int cpu_eth_init(bd_t *bis)
182 #if defined(CONFIG_FEC_MXC)
183 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
185 /* enable FEC clock */
186 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
187 writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
188 return fecmxc_initialize(bis);
195 * Initializes on-chip MMC controllers.
196 * to override, implement board_mmc_init()
198 int cpu_mmc_init(bd_t *bis)
200 #ifdef CONFIG_MMC_MXC
201 return mxc_mmc_init(bis);
207 void imx_gpio_mode(int gpio_mode)
209 struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
210 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
211 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
212 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
213 unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
214 unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
218 if (gpio_mode & GPIO_PUEN) {
219 writel(readl(®s->port[port].puen) | (1 << pin),
220 ®s->port[port].puen);
222 writel(readl(®s->port[port].puen) & ~(1 << pin),
223 ®s->port[port].puen);
227 if (gpio_mode & GPIO_OUT) {
228 writel(readl(®s->port[port].gpio_dir) | 1 << pin,
229 ®s->port[port].gpio_dir);
231 writel(readl(®s->port[port].gpio_dir) & ~(1 << pin),
232 ®s->port[port].gpio_dir);
235 /* Primary / alternate function */
236 if (gpio_mode & GPIO_AF) {
237 writel(readl(®s->port[port].gpr) | (1 << pin),
238 ®s->port[port].gpr);
240 writel(readl(®s->port[port].gpr) & ~(1 << pin),
241 ®s->port[port].gpr);
245 if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
246 writel(readl(®s->port[port].gius) | (1 << pin),
247 ®s->port[port].gius);
249 writel(readl(®s->port[port].gius) & ~(1 << pin),
250 ®s->port[port].gius);
253 /* Output / input configuration */
255 tmp = readl(®s->port[port].ocr1);
256 tmp &= ~(3 << (pin * 2));
257 tmp |= (ocr << (pin * 2));
258 writel(tmp, ®s->port[port].ocr1);
260 writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)),
261 ®s->port[port].iconfa1);
262 writel(readl(®s->port[port].iconfa1) | aout << (pin * 2),
263 ®s->port[port].iconfa1);
264 writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)),
265 ®s->port[port].iconfb1);
266 writel(readl(®s->port[port].iconfb1) | bout << (pin * 2),
267 ®s->port[port].iconfb1);
271 tmp = readl(®s->port[port].ocr2);
272 tmp &= ~(3 << (pin * 2));
273 tmp |= (ocr << (pin * 2));
274 writel(tmp, ®s->port[port].ocr2);
276 writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)),
277 ®s->port[port].iconfa2);
278 writel(readl(®s->port[port].iconfa2) | aout << (pin * 2),
279 ®s->port[port].iconfa2);
280 writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)),
281 ®s->port[port].iconfb2);
282 writel(readl(®s->port[port].iconfb2) | bout << (pin * 2),
283 ®s->port[port].iconfb2);
287 #ifdef CONFIG_MXC_UART
288 void mx27_uart1_init_pins(void)
291 unsigned int mode[] = {
296 for (i = 0; i < ARRAY_SIZE(mode); i++)
297 imx_gpio_mode(mode[i]);
300 #endif /* CONFIG_MXC_UART */
302 #ifdef CONFIG_FEC_MXC
303 void mx27_fec_init_pins(void)
306 unsigned int mode[] = {
316 PD9_AIN_FEC_MDC | GPIO_PUEN,
318 PD11_AOUT_FEC_TX_CLK,
327 for (i = 0; i < ARRAY_SIZE(mode); i++)
328 imx_gpio_mode(mode[i]);
331 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
334 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
335 struct fuse_bank *bank = &iim->bank[0];
336 struct fuse_bank0_regs *fuse =
337 (struct fuse_bank0_regs *)bank->fuse_regs;
339 for (i = 0; i < 6; i++)
340 mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
342 #endif /* CONFIG_FEC_MXC */
344 #ifdef CONFIG_MMC_MXC
345 void mx27_sd1_init_pins(void)
348 unsigned int mode[] = {
357 for (i = 0; i < ARRAY_SIZE(mode); i++)
358 imx_gpio_mode(mode[i]);
362 void mx27_sd2_init_pins(void)
365 unsigned int mode[] = {
374 for (i = 0; i < ARRAY_SIZE(mode); i++)
375 imx_gpio_mode(mode[i]);
378 #endif /* CONFIG_MMC_MXC */