1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
7 #include <asm/arch/cpu.h>
8 #include <asm/arch/clk.h>
9 #include <asm/arch/timer.h>
12 static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE;
13 static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE;
14 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
16 static void lpc32xx_timer_clock(u32 bit, int enable)
19 setbits_le32(&clk->timclk_ctrl1, bit);
21 clrbits_le32(&clk->timclk_ctrl1, bit);
24 static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
26 writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
27 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
28 writel(0, &timer->tc);
29 writel(0, &timer->pr);
31 /* Count mode is every rising PCLK edge */
32 writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
34 /* Set prescale counter value */
35 writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
37 /* Ensure that the counter is not reset when matching TC */
38 writel(0, &timer->mcr);
41 static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
44 writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr);
46 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
51 lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
52 lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
53 lpc32xx_timer_count(timer0, 1);
58 ulong get_timer(ulong base)
60 return readl(&timer0->tc) - base;
63 void __udelay(unsigned long usec)
65 lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
66 lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
67 lpc32xx_timer_count(timer1, 1);
69 while (readl(&timer1->tc) < usec)
72 lpc32xx_timer_count(timer1, 0);
73 lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
76 unsigned long long get_ticks(void)