1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Contributor: Mahavir Jain <mjain@marvell.com>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/armada100.h>
15 #include <linux/delay.h>
19 * Refer Section A.6 in Datasheet
21 struct armd1tmr_registers {
22 u32 clk_ctrl; /* Timer clk control reg */
23 u32 match[9]; /* Timer match registers */
24 u32 count[3]; /* Timer count registers */
27 u32 preload[3]; /* Timer preload value */
35 u32 cer; /* Timer count enable reg */
44 #define TIMER 0 /* Use TIMER 0 */
45 /* Each timer has 3 match registers */
46 #define MATCH_CMP(x) ((3 * TIMER) + x)
47 #define TIMER_LOAD_VAL 0xffffffff
48 #define COUNT_RD_REQ 0x1
50 DECLARE_GLOBAL_DATA_PTR;
51 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
53 /* For preventing risk of instability in reading counter value,
54 * first set read request to register cvwr and then read same
55 * register after it captures counter value.
57 ulong read_timer(void)
59 struct armd1tmr_registers *armd1timers =
60 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
61 volatile int loop=100;
63 writel(COUNT_RD_REQ, &armd1timers->cvwr);
65 return(readl(&armd1timers->cvwr));
68 static ulong get_timer_masked(void)
70 ulong now = read_timer();
72 if (now >= gd->arch.tbl) {
74 gd->arch.tbu += now - gd->arch.tbl;
76 /* we have an overflow ... */
77 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
84 ulong get_timer(ulong base)
86 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
90 void __udelay(unsigned long usec)
95 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
96 endtime = get_timer_masked() + delayticks;
98 while (get_timer_masked() < endtime);
106 struct armd1apb1_registers *apb1clkres =
107 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
108 struct armd1tmr_registers *armd1timers =
109 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
111 /* Enable Timer clock at 3.25 MHZ */
112 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
114 /* load value into timer */
115 writel(0x0, &armd1timers->clk_ctrl);
116 /* Use Timer 0 Match Resiger 0 */
117 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
118 /* Preload value is 0 */
119 writel(0x0, &armd1timers->preload[TIMER]);
120 /* Enable match comparator 0 for Timer 0 */
121 writel(0x1, &armd1timers->preload_ctrl[TIMER]);
124 writel(0x1, &armd1timers->cer);
125 /* init the gd->arch.tbu and gd->arch.tbl value */
126 gd->arch.tbl = read_timer();
132 #define MPMU_APRR_WDTR (1<<4)
133 #define TMR_WFAR 0xbaba /* WDT Register First key */
134 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
137 * This function uses internal Watchdog Timer
138 * based reset mechanism.
139 * Steps to write watchdog registers (protected access)
140 * 1. Write key value to TMR_WFAR reg.
141 * 2. Write key value to TMP_WSAR reg.
142 * 3. Perform write operation.
144 void reset_cpu(unsigned long ignored)
146 struct armd1mpmu_registers *mpmu =
147 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
148 struct armd1tmr_registers *armd1timers =
149 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
152 /* negate hardware reset to the WDT after system reset */
153 val = readl(&mpmu->aprr);
154 val = val | MPMU_APRR_WDTR;
155 writel(val, &mpmu->aprr);
157 /* reset/enable WDT clock */
158 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
159 readl(&mpmu->wdtpcr);
160 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
161 readl(&mpmu->wdtpcr);
163 /* clear previous WDT status */
164 writel(TMR_WFAR, &armd1timers->wfar);
165 writel(TMP_WSAR, &armd1timers->wsar);
166 writel(0, &armd1timers->wdt_sts);
168 /* set match counter */
169 writel(TMR_WFAR, &armd1timers->wfar);
170 writel(TMP_WSAR, &armd1timers->wsar);
171 writel(0xf, &armd1timers->wdt_match_r);
173 /* enable WDT reset */
174 writel(TMR_WFAR, &armd1timers->wfar);
175 writel(TMP_WSAR, &armd1timers->wsar);
176 writel(0x3, &armd1timers->wdt_match_en);
182 * This function is derived from PowerPC code (read timebase as long long).
183 * On ARM it just returns the timer value.
185 unsigned long long get_ticks(void)
191 * This function is derived from PowerPC code (timebase clock frequency).
192 * On ARM it returns the number of timer ticks per second.
194 ulong get_tbclk(void)
196 return (ulong)CONFIG_SYS_HZ;