1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Contributor: Mahavir Jain <mjain@marvell.com>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/armada100.h>
18 * Refer Section A.6 in Datasheet
20 struct armd1tmr_registers {
21 u32 clk_ctrl; /* Timer clk control reg */
22 u32 match[9]; /* Timer match registers */
23 u32 count[3]; /* Timer count registers */
26 u32 preload[3]; /* Timer preload value */
34 u32 cer; /* Timer count enable reg */
43 #define TIMER 0 /* Use TIMER 0 */
44 /* Each timer has 3 match registers */
45 #define MATCH_CMP(x) ((3 * TIMER) + x)
46 #define TIMER_LOAD_VAL 0xffffffff
47 #define COUNT_RD_REQ 0x1
49 DECLARE_GLOBAL_DATA_PTR;
50 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
52 /* For preventing risk of instability in reading counter value,
53 * first set read request to register cvwr and then read same
54 * register after it captures counter value.
56 ulong read_timer(void)
58 struct armd1tmr_registers *armd1timers =
59 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
60 volatile int loop=100;
62 writel(COUNT_RD_REQ, &armd1timers->cvwr);
64 return(readl(&armd1timers->cvwr));
67 static ulong get_timer_masked(void)
69 ulong now = read_timer();
71 if (now >= gd->arch.tbl) {
73 gd->arch.tbu += now - gd->arch.tbl;
75 /* we have an overflow ... */
76 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
83 ulong get_timer(ulong base)
85 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
89 void __udelay(unsigned long usec)
94 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
95 endtime = get_timer_masked() + delayticks;
97 while (get_timer_masked() < endtime);
105 struct armd1apb1_registers *apb1clkres =
106 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
107 struct armd1tmr_registers *armd1timers =
108 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
110 /* Enable Timer clock at 3.25 MHZ */
111 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
113 /* load value into timer */
114 writel(0x0, &armd1timers->clk_ctrl);
115 /* Use Timer 0 Match Resiger 0 */
116 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
117 /* Preload value is 0 */
118 writel(0x0, &armd1timers->preload[TIMER]);
119 /* Enable match comparator 0 for Timer 0 */
120 writel(0x1, &armd1timers->preload_ctrl[TIMER]);
123 writel(0x1, &armd1timers->cer);
124 /* init the gd->arch.tbu and gd->arch.tbl value */
125 gd->arch.tbl = read_timer();
131 #define MPMU_APRR_WDTR (1<<4)
132 #define TMR_WFAR 0xbaba /* WDT Register First key */
133 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
136 * This function uses internal Watchdog Timer
137 * based reset mechanism.
138 * Steps to write watchdog registers (protected access)
139 * 1. Write key value to TMR_WFAR reg.
140 * 2. Write key value to TMP_WSAR reg.
141 * 3. Perform write operation.
143 void reset_cpu(unsigned long ignored)
145 struct armd1mpmu_registers *mpmu =
146 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
147 struct armd1tmr_registers *armd1timers =
148 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
151 /* negate hardware reset to the WDT after system reset */
152 val = readl(&mpmu->aprr);
153 val = val | MPMU_APRR_WDTR;
154 writel(val, &mpmu->aprr);
156 /* reset/enable WDT clock */
157 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
158 readl(&mpmu->wdtpcr);
159 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
160 readl(&mpmu->wdtpcr);
162 /* clear previous WDT status */
163 writel(TMR_WFAR, &armd1timers->wfar);
164 writel(TMP_WSAR, &armd1timers->wsar);
165 writel(0, &armd1timers->wdt_sts);
167 /* set match counter */
168 writel(TMR_WFAR, &armd1timers->wfar);
169 writel(TMP_WSAR, &armd1timers->wsar);
170 writel(0xf, &armd1timers->wdt_match_r);
172 /* enable WDT reset */
173 writel(TMR_WFAR, &armd1timers->wfar);
174 writel(TMP_WSAR, &armd1timers->wsar);
175 writel(0x3, &armd1timers->wdt_match_en);
181 * This function is derived from PowerPC code (read timebase as long long).
182 * On ARM it just returns the timer value.
184 unsigned long long get_ticks(void)
190 * This function is derived from PowerPC code (timebase clock frequency).
191 * On ARM it returns the number of timer ticks per second.
193 ulong get_tbclk(void)
195 return (ulong)CONFIG_SYS_HZ;