2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
13 * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/bitops.h>
25 #include <net/genetlink.h>
26 #include <linux/switch.h>
27 #include <linux/delay.h>
28 #include <linux/phy.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/lockdep.h>
32 #include <linux/workqueue.h>
33 #include <linux/of_device.h>
37 #define MT7530_CPU_PORT 6
38 #define MT7530_NUM_PORTS 8
39 #ifdef CONFIG_SOC_MT7621
40 #define MT7530_NUM_VLANS 4095
42 #define MT7530_NUM_VLANS 16
44 #define MT7530_MAX_VID 4095
45 #define MT7530_MIN_VID 0
47 #define MT7530_PORT_MIB_TXB_ID 2 /* TxGOC */
48 #define MT7530_PORT_MIB_RXB_ID 6 /* RxGOC */
50 #define MT7621_PORT_MIB_TXB_ID 18 /* TxByte */
51 #define MT7621_PORT_MIB_RXB_ID 37 /* RxByte */
54 #define REG_ESW_WT_MAC_MFC 0x10
56 #define REG_ESW_WT_MAC_MFC_MIRROR_ENABLE BIT(3)
57 #define REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK 0x07
59 #define REG_ESW_VLAN_VTCR 0x90
60 #define REG_ESW_VLAN_VAWD1 0x94
61 #define REG_ESW_VLAN_VAWD2 0x98
62 #define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
64 #define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
65 #define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
66 #define REG_ESW_VLAN_VAWD1_VALID BIT(0)
68 /* vlan egress mode */
76 #define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
77 #define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
78 #define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
80 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT BIT(8)
81 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT BIT(9)
82 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_MASK 0x0100
83 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_MASK 0x0200
85 #define REG_HWTRAP 0x7804
87 #define MIB_DESC(_s , _o, _n) \
94 struct mt7xxx_mib_desc {
100 static const struct mt7xxx_mib_desc mt7620_mibs[] = {
101 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
102 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
103 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
104 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
105 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
106 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
107 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
108 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
109 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
110 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
111 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
112 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
113 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
114 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
115 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
116 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
117 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
118 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
119 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
120 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
121 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
122 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
123 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
124 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
125 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
126 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
127 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
128 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
129 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
130 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
133 static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
134 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
135 MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
136 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
137 MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
138 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
139 MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
140 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
141 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
142 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
145 static const struct mt7xxx_mib_desc mt7621_mibs[] = {
146 MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
147 MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
148 MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
149 MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
150 MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
151 MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
152 MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
153 MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
154 MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
155 MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
156 MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
157 MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
158 MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
159 MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
160 MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
161 MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
162 MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
163 MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
164 MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
165 MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
166 MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
167 MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
168 MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
169 MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
170 MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
171 MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
172 MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
173 MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
174 MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
175 MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
176 MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
177 MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
178 MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
179 MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
180 MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
181 MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
182 MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
183 MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
184 MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
185 MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
186 MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
190 /* Global attributes. */
191 MT7530_ATTR_ENABLE_VLAN,
194 struct mt7530_port_entry {
200 struct mt7530_vlan_entry {
209 struct switch_dev swdev;
213 bool global_vlan_enable;
214 struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
215 struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
218 struct mt7530_mapping {
220 u16 pvids[MT7530_NUM_PORTS];
221 u8 members[MT7530_NUM_VLANS];
222 u8 etags[MT7530_NUM_VLANS];
223 u16 vids[MT7530_NUM_VLANS];
224 } mt7530_defaults[] = {
227 .pvids = { 1, 1, 1, 1, 2, 1, 1 },
228 .members = { 0, 0x6f, 0x50 },
229 .etags = { 0, 0x40, 0x40 },
233 .pvids = { 2, 1, 1, 1, 1, 1, 1 },
234 .members = { 0, 0x7e, 0x41 },
235 .etags = { 0, 0x40, 0x40 },
239 .pvids = { 1, 2, 1, 1, 1, 1, 1 },
240 .members = { 0, 0x7d, 0x42 },
241 .etags = { 0, 0x40, 0x40 },
246 struct mt7530_mapping*
247 mt7530_find_mapping(struct device_node *np)
252 if (of_property_read_string(np, "mediatek,portmap", &map))
255 for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
256 if (!strcmp(map, mt7530_defaults[i].name))
257 return &mt7530_defaults[i];
263 mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
267 for (i = 0; i < MT7530_NUM_PORTS; i++)
268 mt7530->port_entries[i].pvid = map->pvids[i];
270 for (i = 0; i < MT7530_NUM_VLANS; i++) {
271 mt7530->vlan_entries[i].member = map->members[i];
272 mt7530->vlan_entries[i].etags = map->etags[i];
273 mt7530->vlan_entries[i].vid = map->vids[i];
278 mt7530_reset_switch(struct switch_dev *dev)
280 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
283 memset(priv->port_entries, 0, sizeof(priv->port_entries));
284 memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
286 /* set default vid of each vlan to the same number of vlan, so the vid
287 * won't need be set explicitly.
289 for (i = 0; i < MT7530_NUM_VLANS; i++) {
290 priv->vlan_entries[i].vid = i;
297 mt7530_get_vlan_enable(struct switch_dev *dev,
298 const struct switch_attr *attr,
299 struct switch_val *val)
301 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
303 val->value.i = priv->global_vlan_enable;
309 mt7530_set_vlan_enable(struct switch_dev *dev,
310 const struct switch_attr *attr,
311 struct switch_val *val)
313 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
315 priv->global_vlan_enable = val->value.i != 0;
321 mt7530_r32(struct mt7530_priv *priv, u32 reg)
327 mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
328 low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
329 high = mdiobus_read(priv->bus, 0x1f, 0x10);
331 return (high << 16) | (low & 0xffff);
334 val = ioread32(priv->base + reg);
335 pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
341 mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
344 mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
345 mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
346 mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
350 pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
351 iowrite32(val, priv->base + reg);
355 mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
359 mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
361 for (i = 0; i < 20; i++) {
362 u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
364 if ((val & BIT(31)) == 0)
370 printk("mt7530: vtcr timeout\n");
374 mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
376 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
378 if (port >= MT7530_NUM_PORTS)
381 *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
388 mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
390 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
392 if (port >= MT7530_NUM_PORTS)
395 if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
398 priv->port_entries[port].pvid = pvid;
404 mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
406 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
413 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
416 mt7530_vtcr(priv, 0, val->port_vlan);
418 member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
422 etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
424 for (i = 0; i < MT7530_NUM_PORTS; i++) {
425 struct switch_port *p;
428 if (!(member & BIT(i)))
431 p = &val->value.ports[val->len++];
434 etag = (etags >> (i * 2)) & 0x3;
436 if (etag == ETAG_CTRL_TAG)
437 p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
438 else if (etag != ETAG_CTRL_UNTAG)
439 printk("vlan egress tag control neither untag nor tag.\n");
446 mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
448 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
453 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
454 val->len > MT7530_NUM_PORTS)
457 for (i = 0; i < val->len; i++) {
458 struct switch_port *p = &val->value.ports[i];
460 if (p->id >= MT7530_NUM_PORTS)
463 member |= BIT(p->id);
465 if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
468 priv->vlan_entries[val->port_vlan].member = member;
469 priv->vlan_entries[val->port_vlan].etags = etags;
475 mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
476 struct switch_val *val)
478 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
482 vlan = val->port_vlan;
483 vid = (u16)val->value.i;
485 if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
488 if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
491 priv->vlan_entries[vlan].vid = vid;
496 mt7621_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
497 struct switch_val *val)
499 val->value.i = val->port_vlan;
504 mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
505 struct switch_val *val)
507 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
511 vlan = val->port_vlan;
513 vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
523 mt7530_get_mirror_rx_enable(struct switch_dev *dev, const struct switch_attr *attr,
524 struct switch_val *val)
526 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
528 val->value.i = priv->port_entries[priv->mirror_src_port].mirror_rx;
534 mt7530_set_mirror_rx_enable(struct switch_dev *dev, const struct switch_attr *attr,
535 struct switch_val *val)
537 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
539 priv->port_entries[priv->mirror_src_port].mirror_rx = val->value.i;
545 mt7530_get_mirror_tx_enable(struct switch_dev *dev, const struct switch_attr *attr,
546 struct switch_val *val)
548 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
550 val->value.i = priv->port_entries[priv->mirror_src_port].mirror_tx;
556 mt7530_set_mirror_tx_enable(struct switch_dev *dev, const struct switch_attr *attr,
557 struct switch_val *val)
559 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
561 priv->port_entries[priv->mirror_src_port].mirror_tx = val->value.i;
567 mt7530_get_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,
568 struct switch_val *val)
570 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
572 val->value.i = priv->mirror_dest_port;
578 mt7530_set_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,
579 struct switch_val *val)
581 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
583 priv->mirror_dest_port = val->value.i;
589 mt7530_get_mirror_source_port(struct switch_dev *dev, const struct switch_attr *attr,
590 struct switch_val *val)
592 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
594 val->value.i = priv->mirror_src_port;
600 mt7530_set_mirror_source_port(struct switch_dev *dev, const struct switch_attr *attr,
601 struct switch_val *val)
603 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
605 priv->mirror_src_port = val->value.i;
611 mt7530_get_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
612 struct switch_val *val)
614 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
616 val->value.i = priv->port_entries[val->port_vlan].mirror_rx;
622 mt7530_set_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
623 struct switch_val *val)
625 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
627 priv->port_entries[val->port_vlan].mirror_rx = val->value.i;
633 mt7530_get_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
634 struct switch_val *val)
636 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
638 val->value.i = priv->port_entries[val->port_vlan].mirror_tx;
644 mt7530_set_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
645 struct switch_val *val)
647 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
649 priv->port_entries[val->port_vlan].mirror_tx = val->value.i;
655 mt7530_write_vlan_entry(struct mt7530_priv *priv, int vlan, u16 vid,
661 #ifndef CONFIG_SOC_MT7621
663 val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
671 mt7530_w32(priv, REG_ESW_VLAN_VTIM(vlan), val);
674 /* vlan port membership */
676 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
677 REG_ESW_VLAN_VAWD1_VTAG_EN | (ports << 16) |
678 REG_ESW_VLAN_VAWD1_VALID);
680 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
684 for (port = 0; port < MT7530_NUM_PORTS; port++) {
685 if (etags & BIT(port))
686 val |= ETAG_CTRL_TAG << (port * 2);
688 val |= ETAG_CTRL_UNTAG << (port * 2);
690 mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
692 /* write to vlan table */
693 #ifdef CONFIG_SOC_MT7621
694 mt7530_vtcr(priv, 1, vid);
696 mt7530_vtcr(priv, 1, vlan);
701 mt7530_apply_config(struct switch_dev *dev)
703 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
707 bool is_mirror = false;
709 if (!priv->global_vlan_enable) {
710 for (i = 0; i < MT7530_NUM_PORTS; i++)
711 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
713 mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
715 for (i = 0; i < MT7530_NUM_PORTS; i++)
716 mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
721 /* set all ports as security mode */
722 for (i = 0; i < MT7530_NUM_PORTS; i++)
723 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
725 /* check if a port is used in tag/untag vlan egress mode */
729 for (i = 0; i < MT7530_NUM_VLANS; i++) {
730 u8 member = priv->vlan_entries[i].member;
731 u8 etags = priv->vlan_entries[i].etags;
736 for (j = 0; j < MT7530_NUM_PORTS; j++) {
737 if (!(member & BIT(j)))
741 tag_ports |= 1u << j;
743 untag_ports |= 1u << j;
747 /* set all untag-only ports as transparent and the rest as user port */
748 for (i = 0; i < MT7530_NUM_PORTS; i++) {
749 u32 pvc_mode = 0x81000000;
751 if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
752 pvc_mode = 0x810000c0;
754 mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
757 /* first clear the swtich vlan table */
758 for (i = 0; i < MT7530_NUM_VLANS; i++)
759 mt7530_write_vlan_entry(priv, i, i, 0, 0);
761 /* now program only vlans with members to avoid
762 clobbering remapped entries in later iterations */
763 for (i = 0; i < MT7530_NUM_VLANS; i++) {
764 u16 vid = priv->vlan_entries[i].vid;
765 u8 member = priv->vlan_entries[i].member;
766 u8 etags = priv->vlan_entries[i].etags;
769 mt7530_write_vlan_entry(priv, i, vid, member, etags);
772 /* Port Default PVID */
773 for (i = 0; i < MT7530_NUM_PORTS; i++) {
774 int vlan = priv->port_entries[i].pvid;
778 if (vlan < MT7530_NUM_VLANS && priv->vlan_entries[vlan].member)
779 pvid = priv->vlan_entries[vlan].vid;
781 val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
784 mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
787 /* set mirroring source port */
788 for (i = 0; i < MT7530_NUM_PORTS; i++) {
789 u32 val = mt7530_r32(priv, REG_ESW_PORT_PCR(i));
790 if (priv->port_entries[i].mirror_rx) {
791 val |= REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT;
795 if (priv->port_entries[i].mirror_tx) {
796 val |= REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT;
800 mt7530_w32(priv, REG_ESW_PORT_PCR(i), val);
803 /* set mirroring monitor port */
805 u32 val = mt7530_r32(priv, REG_ESW_WT_MAC_MFC);
806 val |= REG_ESW_WT_MAC_MFC_MIRROR_ENABLE;
807 val &= ~REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK;
808 val |= priv->mirror_dest_port;
809 mt7530_w32(priv, REG_ESW_WT_MAC_MFC, val);
816 mt7530_get_port_link(struct switch_dev *dev, int port,
817 struct switch_port_link *link)
819 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
822 if (port < 0 || port >= MT7530_NUM_PORTS)
825 pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
827 link->link = pmsr & 1;
828 link->duplex = (pmsr >> 1) & 1;
829 speed = (pmsr >> 2) & 3;
833 link->speed = SWITCH_PORT_SPEED_10;
836 link->speed = SWITCH_PORT_SPEED_100;
839 case 3: /* forced gige speed can be 2 or 3 */
840 link->speed = SWITCH_PORT_SPEED_1000;
843 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
850 static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
852 unsigned int port_base;
855 port_base = MT7621_MIB_COUNTER_BASE +
856 MT7621_MIB_COUNTER_PORT_OFFSET * port;
858 lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
859 if (mt7621_mibs[i].size == 2) {
862 hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
869 static int mt7621_sw_get_port_mib(struct switch_dev *dev,
870 const struct switch_attr *attr,
871 struct switch_val *val)
873 static char buf[4096];
874 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
877 if (val->port_vlan >= MT7530_NUM_PORTS)
880 len += snprintf(buf + len, sizeof(buf) - len,
881 "Port %d MIB counters\n", val->port_vlan);
883 for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
885 len += snprintf(buf + len, sizeof(buf) - len,
886 "%-11s: ", mt7621_mibs[i].name);
887 counter = get_mib_counter(priv, i, val->port_vlan);
888 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
897 static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
899 return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
902 static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
904 return mt7530_r32(priv,
905 MT7620_MIB_COUNTER_BASE_PORT +
906 (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
907 mt7620_port_mibs[i].offset);
910 static int mt7530_sw_get_mib(struct switch_dev *dev,
911 const struct switch_attr *attr,
912 struct switch_val *val)
914 static char buf[4096];
915 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
918 len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
920 for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
922 len += snprintf(buf + len, sizeof(buf) - len,
923 "%-11s: ", mt7620_mibs[i].name);
924 counter = get_mib_counter_7620(priv, i);
925 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
934 static int mt7530_sw_get_port_mib(struct switch_dev *dev,
935 const struct switch_attr *attr,
936 struct switch_val *val)
938 static char buf[4096];
939 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
942 if (val->port_vlan >= MT7530_NUM_PORTS)
945 len += snprintf(buf + len, sizeof(buf) - len,
946 "Port %d MIB counters\n", val->port_vlan);
948 for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
950 len += snprintf(buf + len, sizeof(buf) - len,
951 "%-11s: ", mt7620_port_mibs[i].name);
952 counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
953 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
962 static int mt7530_get_port_stats(struct switch_dev *dev, int port,
963 struct switch_port_stats *stats)
965 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
967 if (port < 0 || port >= MT7530_NUM_PORTS)
970 stats->tx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_TXB_ID, port);
971 stats->rx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_RXB_ID, port);
976 static int mt7621_get_port_stats(struct switch_dev *dev, int port,
977 struct switch_port_stats *stats)
979 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
981 if (port < 0 || port >= MT7530_NUM_PORTS)
984 stats->tx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_TXB_ID, port);
985 stats->rx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_RXB_ID, port);
990 static const struct switch_attr mt7530_global[] = {
992 .type = SWITCH_TYPE_INT,
993 .name = "enable_vlan",
994 .description = "VLAN mode (1:enabled)",
996 .id = MT7530_ATTR_ENABLE_VLAN,
997 .get = mt7530_get_vlan_enable,
998 .set = mt7530_set_vlan_enable,
1000 .type = SWITCH_TYPE_STRING,
1002 .description = "Get MIB counters for switch",
1003 .get = mt7530_sw_get_mib,
1006 .type = SWITCH_TYPE_INT,
1007 .name = "enable_mirror_rx",
1008 .description = "Enable mirroring of RX packets",
1009 .set = mt7530_set_mirror_rx_enable,
1010 .get = mt7530_get_mirror_rx_enable,
1013 .type = SWITCH_TYPE_INT,
1014 .name = "enable_mirror_tx",
1015 .description = "Enable mirroring of TX packets",
1016 .set = mt7530_set_mirror_tx_enable,
1017 .get = mt7530_get_mirror_tx_enable,
1020 .type = SWITCH_TYPE_INT,
1021 .name = "mirror_monitor_port",
1022 .description = "Mirror monitor port",
1023 .set = mt7530_set_mirror_monitor_port,
1024 .get = mt7530_get_mirror_monitor_port,
1025 .max = MT7530_NUM_PORTS - 1
1027 .type = SWITCH_TYPE_INT,
1028 .name = "mirror_source_port",
1029 .description = "Mirror source port",
1030 .set = mt7530_set_mirror_source_port,
1031 .get = mt7530_get_mirror_source_port,
1032 .max = MT7530_NUM_PORTS - 1
1036 static const struct switch_attr mt7621_port[] = {
1038 .type = SWITCH_TYPE_STRING,
1040 .description = "Get MIB counters for port",
1041 .get = mt7621_sw_get_port_mib,
1044 .type = SWITCH_TYPE_INT,
1045 .name = "enable_mirror_rx",
1046 .description = "Enable mirroring of RX packets",
1047 .set = mt7530_set_port_mirror_rx,
1048 .get = mt7530_get_port_mirror_rx,
1051 .type = SWITCH_TYPE_INT,
1052 .name = "enable_mirror_tx",
1053 .description = "Enable mirroring of TX packets",
1054 .set = mt7530_set_port_mirror_tx,
1055 .get = mt7530_get_port_mirror_tx,
1060 static const struct switch_attr mt7621_vlan[] = {
1062 .type = SWITCH_TYPE_INT,
1064 .description = "VLAN ID (0-4094)",
1065 .set = mt7530_set_vid,
1066 .get = mt7621_get_vid,
1071 static const struct switch_attr mt7530_port[] = {
1073 .type = SWITCH_TYPE_STRING,
1075 .description = "Get MIB counters for port",
1076 .get = mt7530_sw_get_port_mib,
1079 .type = SWITCH_TYPE_INT,
1080 .name = "enable_mirror_rx",
1081 .description = "Enable mirroring of RX packets",
1082 .set = mt7530_set_port_mirror_rx,
1083 .get = mt7530_get_port_mirror_rx,
1086 .type = SWITCH_TYPE_INT,
1087 .name = "enable_mirror_tx",
1088 .description = "Enable mirroring of TX packets",
1089 .set = mt7530_set_port_mirror_tx,
1090 .get = mt7530_get_port_mirror_tx,
1095 static const struct switch_attr mt7530_vlan[] = {
1097 .type = SWITCH_TYPE_INT,
1099 .description = "VLAN ID (0-4094)",
1100 .set = mt7530_set_vid,
1101 .get = mt7530_get_vid,
1106 static const struct switch_dev_ops mt7621_ops = {
1108 .attr = mt7530_global,
1109 .n_attr = ARRAY_SIZE(mt7530_global),
1112 .attr = mt7621_port,
1113 .n_attr = ARRAY_SIZE(mt7621_port),
1116 .attr = mt7621_vlan,
1117 .n_attr = ARRAY_SIZE(mt7621_vlan),
1119 .get_vlan_ports = mt7530_get_vlan_ports,
1120 .set_vlan_ports = mt7530_set_vlan_ports,
1121 .get_port_pvid = mt7530_get_port_pvid,
1122 .set_port_pvid = mt7530_set_port_pvid,
1123 .get_port_link = mt7530_get_port_link,
1124 .get_port_stats = mt7621_get_port_stats,
1125 .apply_config = mt7530_apply_config,
1126 .reset_switch = mt7530_reset_switch,
1129 static const struct switch_dev_ops mt7530_ops = {
1131 .attr = mt7530_global,
1132 .n_attr = ARRAY_SIZE(mt7530_global),
1135 .attr = mt7530_port,
1136 .n_attr = ARRAY_SIZE(mt7530_port),
1139 .attr = mt7530_vlan,
1140 .n_attr = ARRAY_SIZE(mt7530_vlan),
1142 .get_vlan_ports = mt7530_get_vlan_ports,
1143 .set_vlan_ports = mt7530_set_vlan_ports,
1144 .get_port_pvid = mt7530_get_port_pvid,
1145 .set_port_pvid = mt7530_set_port_pvid,
1146 .get_port_link = mt7530_get_port_link,
1147 .get_port_stats = mt7530_get_port_stats,
1148 .apply_config = mt7530_apply_config,
1149 .reset_switch = mt7530_reset_switch,
1153 mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
1155 struct switch_dev *swdev;
1156 struct mt7530_priv *mt7530;
1157 struct mt7530_mapping *map;
1160 mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
1164 mt7530->base = base;
1166 mt7530->global_vlan_enable = vlan;
1168 swdev = &mt7530->swdev;
1170 swdev->alias = "mt7530";
1171 swdev->name = "mt7530";
1172 } else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
1173 swdev->alias = "mt7621";
1174 swdev->name = "mt7621";
1176 swdev->alias = "mt7620";
1177 swdev->name = "mt7620";
1179 swdev->cpu_port = MT7530_CPU_PORT;
1180 swdev->ports = MT7530_NUM_PORTS;
1181 swdev->vlans = MT7530_NUM_VLANS;
1182 if (IS_ENABLED(CONFIG_SOC_MT7621))
1183 swdev->ops = &mt7621_ops;
1185 swdev->ops = &mt7530_ops;
1187 ret = register_switch(swdev, NULL);
1189 dev_err(dev, "failed to register mt7530\n");
1194 map = mt7530_find_mapping(dev->of_node);
1196 mt7530_apply_mapping(mt7530, map);
1197 mt7530_apply_config(swdev);
1200 if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
1201 dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
1202 mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
1204 dev_info(dev, "loaded %s driver\n", swdev->name);